PCIe 5.0 testing ensures accurate BER analysis
Article By : Hiroshi Goto
Higher speeds of 32 GT/sec bring on more signal integrity issues.
The release of the PCIe 5.0 specification earlier this year by the PCI-SIG was welcomed by designers of emerging applications such as artificial intelligence (AI), as well as engineers responsible for current high-bandwidth environments, particularly data centers, networking, and high performance computing (HPC). While the PCIe 5.0 specification is a seemingly natural extension of PCIe 4.0 architecture, there are test aspects that engineers must be aware of to ensure compliance and compatibility.
To address signal degradation, stricter requirements in channel and connector loss and reflections have been implemented, as well as slight improvements in receiver and transmitter equalization. Also, the data rate has been doubled from 16 GT/s to 32 GT/s with no major innovations to compensate for issues created by steeper rise-fall times, narrower unit intervals (UIs), and greater insertion loss.
[See What does GT/s mean, anyway?]
Need for comprehensive serdes tests
To ensure PCIe 5.0 technology designs are compliant (which means products have passed the PCI-SIG interoperability testing at PCI-SIG hosted compliance workshops), engineers must conduct comprehensive serdes tests. PCIe 5.0 testing requires a bit-error ratio tester (BERT) pulse pattern generator (PPG) that can apply precise levels of specific signal impairments and a BERT error detector (ED) that can analyze the serdes output bit error ratio (BER). A real-time oscilloscope with sampling bandwidth of >50 GHz is also necessary.
For the most complicated serdes test, link equalization training, the BERT must emulate a reference serdes. The PPG and ED must interact with the device under test (DUT) at the PHY logical sub-block level of the PCIe 5.0 protocol stack (Figure 1).
Figure 1 The PCIe 5.0 protocol stack consists of several layers.
Challenge of NRZ at 32 GT/s
The biggest challenge in advancing from PCIe 4.0 architecture at 16 GT/s to PCIe 5.0 architecture at 32 GT/s is the ability to function with up to 36 dB of loss at the prescribed BER ≤ 10-12. To mitigate problems associated with loss, most standards that operate in excess of 30 GT/s have adopted PAM-4 to reduce operating bandwidth by a factor of two at the expense of over 9.5 dB in reduced signal-to-noise ratio. PCIe 5.0 technology, however, continues to operate with the logic-emulating, baseband non-return to zero (NRZ) modulation scheme that has high levels for logic 1s and low levels for logic 0s.
With so much loss, a compliant PCIe 5.0 architecture post-equalization eye opening can be as low as 10 mV. Such a small voltage swing requires extremely sensitive voltage slicers. To accommodate long reaches of a circuit board, retimers are required when loss exceeds -36 dB or when the signal propagates through two or more connectors.
Inter-symbol interference and equalization
Link training corrects inter-symbol interference (ISI) in PCIe 5.0 technology. It involves communication between the receiver and transmitter to optimize and coordinate the adjustable equalization parameters – feed-forward equalizer (FFE) taps at the transmitter and continuous time linear equalizer (CTLE) gain and decision feedback equalizer (DFE) taps at the receiver.
Transmitter FFE pre-distorts the waveform in a manner that partially compensates for the distortion caused by the channel frequency response. Jitter, noise, distortion, crosstalk, and intersymbol interference (ISI) present ever greater design challenges with each increment in PCIe technology rate. PCIe 5.0 eye diagrams are fully closed at the receiver input. To achieve BER ≤ 10-12, receivers have become more sophisticated with clock recovery, multiple equalization schemes at both the transmitter and receiver, sensitive slicers, and the ability to evaluate their own BER performance.
Jitter requirements are the same in PCIe 4.0 and PCIe 5.0 architectures as measured in UI but are proportionally tighter when measured in picoseconds. Therefore, the distributed reference clock, or common clock (CC) architecture, optional in PCIe 4.0 specification, is now required in PCIe 5.0 specification.
The greatest difficulties in advancing from 16 GT/s to 32 GT/s are caused by the maximum allowed loss increasing from -28 dB to -36 dB. As a result, PCIe 5.0 channel requirements have been redefined so only surface mount connectors are allowed for add-in cards in the card electro-mechanical (CEM) specification.
Initial transmitter equalization test
To conduct an initial transmitter equalization test, the BERT PPG sends requests to the DUT-transmitter through the PCIe technology physical layer logic-sub-block protocol. The BERT PPG sequentially sends requests to the DUT-serdes for every feed-forward equalization (FFE) preset at each PCIe architecture data rate. The DUT-transmitter modifies its FFE scheme and transmits the signals.
The DUT-transmitter output is split so that its signal is sent to the oscilloscope and BERT ED. Serving as the reference receiver, the BERT ED confirms the preset change and the BERT serving as the PPG auxiliary output triggers the oscilloscope acquisition of each signal. The oscilloscope captures the waveforms with every FFE preset and data rate. It then runs SigTest, easily-installed software available from the PCI-SIG, to evaluate each waveform according to the compliance requirements and displays the results.
Transmitter link equalization response test
The transmitter link equalization response test measures the time for the DUT transmitter to respond to FFE tap requests and determine whether the response is correct. The BERT is the reference serdes in loopback mode. The oscilloscope determines the time, tREQ, of the request and the time that the FFE taps change, tCHANGE. The elapsed time must be less than or equal to the specified maximum, 500 ns for the BASE specification and 1 µs for the CEM specification.
Figure 2 This is the transmitter link equalization response test configuration.
Figure 2 shows the test set-up. The BERT PPG differential output is split so that the signal is transmitted to the DUT-receiver and the oscilloscope. The DUT-transmitter output is also divided so its signal is sent to the oscilloscope and the BERT ED in its role as reference receiver.
Receiver link equalization test
PCIe 5.0 technology receivers have one compliance test at the PHY level. Link training and stressed receiver tolerance are evaluated simultaneously by using a stressed signal in the link equalization test. The BERT PPG transmits a test signal that includes random jitter (RJ) and sinusoidal jitter (SJ), as well as sinusoidal differential mode interference (DMI) and common mode interference (CMI). A variable ISI test board with several differential trace lengths with losses of 34 dB to 37 dB in 0.5-dB steps applies various amounts of loss and ISI. Calibration of the test signal is performed by the oscilloscope.
The BERT PPG transmits a signal with interference noise to the variable ISI board, whose output is connected to the compliance base board (CBB) to emulate the worst-case performance of the system board. The test signal propagates across the CBB to the CEM connector and then to the add-in card to the DUT-receiver. The BERT PPG applies jitter to the signal through the reference clock. The DUT-transmitter output is sent to the BERT ED, which measures BER and acts as the reference receiver for link training.
Stressed eye calibration
Calibration of the stressed signal involves application of signal impairments and optimization of the continuous-time linear equalization (CTLE). The stressed signal must be calibrated for each BERT PPG preset and every set of FFE taps must comply with the specification. To maximize the stress on the equalization scheme, the signal impairments should be evaluated in a specific order. The required level of RJ and the allowed ranges of loss, SJ, DMI, and CMI that can be added to the signal to achieve the desired EH12 and EW12.
Receiver link equalization BER test
Once the BERT PPG reference transmitter is configured and calibrated with worst case stress and optimized FFE, the receiver link equalization test is comparatively easy. The DUT-serdes follows the link training status and state machine (LTSSM) that configures the system to operate at the maximum data rate possible (Figure 3). The DUT-receiver detects the transmitted signal from the BERT PPG and goes into loopback mode.
Figure 3 LTSSM configures the system to operate at the highest data rate possible in the channel.
Once in loopback mode, the DUT-transmitter requests FFE presets of the BERT PPG. The DUT works through the LTSSM, optimizing link equalization by modifying its receiver equalization scheme as it auditions different BERT PPG FFE presets.
The BERT ED monitors the BER through the process. The BER test takes about a minute, enough time for a PCIe 5.0 system to transmit 2×1012 bits. Since PCIe 5.0 specification designates receiver performance but not equalization technology, it’s possible for the final presets to differ from those obtained during calibration. The DUT must have a BER of < 10-12, as shown in Figure 4, to be compliant with the PCIe 5.0 specification.
Transmitter PLL bandwidth test
PCIe 5.0 transmitters operate with a 100 MHz reference clock (RefClck). A Phase Locked Loop (PLL) is used to multiply the reference clock to the data rate. The data rate clock is used by the serializer to latch lower rate data into a PCIe-compliant high-speed serial data signal.
The PLL bandwidth test measures the DUT-transmitter jitter transfer function. The PLL bandwidth test verifies that the add-in card PLL bandwidth and peaking are within allowed limits and is required by the CEM add-in card specification.
Figure 4 Here are the results of a PCIe 5.0 technology receiver link equalization BER test displayed on the Anritsu MP1900A.
The -3 dB roll off of the DUT receiver must be within the specified frequency range and not exhibit excessive peaking. A complementary relationship exists between the transmitter PLL and the receiver clock-data recovery (CDR) circuit. Since receivers are robust to jitter at frequencies below their CDR bandwidth and susceptible to jitter at frequencies above the CDR bandwidth, the transmitter PLL must filter jitter at high frequencies for the system to operate at the required BER.
The test is performed using the BERT subrate clock output to apply SJ to the DUT reference clock. The idea is to apply calibrated amplitudes of SJ at frequencies that span the specified PLL rolloff frequency and measure the DUT-transmitter output jitter for each.
An oscilloscope calibrates applied SJ amplitudes at frequencies that span the PLL rolloff. The oscilloscope measures the output periodic jitter (PJ) amplitude for each frequency of applied SJ. PCIe 5.0 specifies the allowed range of frequencies in which the -3 dB rolloff must occur and the allowed range of peak jitter amplitudes.
Receiver jitter tolerance test
The jitter tolerance test (JTOL) is the receiver complement to the transmitter PLL bandwidth test. JTOL is not required by the PCIe 5.0 specification, but it is an excellent way to evaluate a receiver’s ability to tolerate different amplitudes and frequencies of jitter.
The stressed signal is, again, the worst case but compliant signal—complete with ISI, random jitter (RJ), DMI, and CMI. As a debug technique or performance margin analysis, JTOL can be tested with any equalization scheme. SJ is then added to the signal according to the amplitude-frequency template (Figure 5).
Figure 5 Amplitude-frequency template
High amplitude jitter is applied at low frequencies and low amplitude jitter at high frequencies. The 1 MHz to 10 MHz rolloff follows the specified CDR frequency response. BER is measured across the template. DUT-receivers should adhere to BER ≤ 10-12 for all amplitude-frequency pairs.
Hiroshi Goto is the high-speed and optical product manager and business development manager at Anritsu Company.
