# Power Tips #95: Optimize efficiency in an active-clamp flyback design

#### Article By : Sarmad Abedin, Texas Instruments Optimize the active-clamp flyback topology for higher efficiencies by reducing the switch-node capacitance and using a secondary resonance circuit.

With the ever-growing demand of electronic devices to do more processing in a smaller package, the top priority on any power supply these days is power density. The most popular isolated power supply topology is the flyback, but the leakage and switching losses of a traditional flyback limit the switching frequency and prevent the ability to achieve a small solution size. Fortunately, there are new ways to optimize the flyback topology to produce much higher efficiencies, even while switching at a higher frequency.

One key component that limits the efficiency of the traditional flyback topology is the passive clamp. This is a resistor-capacitor diode (RCD) network placed from the switch node to the input voltage. Its purpose is to dissipate the transformer leakage inductance and relieve voltage stress on the primary field-effect transistor (FET). The issue is that all the leakage energy is wasted and produces loss.

A popular variant of this clamping method is the active-clamp flyback (Figure 1). It replaces the passive RCD clamp with an active FET and a clamp capacitor. This configuration makes it possible to store the leakage energy in the capacitor and carefully transfer it to the output later in the switching cycle, thus increasing efficiency. Figure 1 The active-clamp flyback improves efficiency in isolated power supply design.

Another benefit to having an active clamp is that you can have current flow both ways through the clamp FET, which enables zero-voltage switching (ZVS) of the primary FET (QL from Figure 1).

To understand the importance of this ZVS, you must first analyze the switching losses in QL. Equation 1 calculates QL‘s turn-on loss of (the majority of total switching loss) when discharging the switch node’s (QL‘s drain’s) parasitic capacitance:

PLOSS_SW =1/2 × Csw_total × (Vsw)2 × fsw (Equation 1)

where Csw_total is the switch node’s total capacitance at turn-on, VSW is the voltage at the switch node upon turn-on, and fSW is the switching frequency.

Because turn-on switching losses are virtually eliminated when VSW is close to zero, it’s possible to switch faster without increasing switching losses. If the active-clamp flyback is operating in transition mode, you can use QH (from Figure 1) to build up some negative magnetizing current in the transformer’s primary winding, then use that current to discharge the switch-node capacitance.

In addition to the leakage energy, the clamp capacitor also holds some of the magnetizing energy. As shown in Figure 2, adjusting the on-time of QH allows negative magnetizing current (Im-) to flow and discharge the switch node to zero before QL turns on. Figure 2 Developing some negative magnetizing current (Im-) helps achieve zero-voltage switching (yellow: VSW; blue: primary current; green: secondary current)

The amount of Im- must be just large enough to achieve ZVS and not more. Equation 2 gives the minimum amount of Im- as:

Im- = – √(Csw_total /Lm ) × Vin (Equation 2)

Excess negative current will result in higher core loss and a lower operating frequency. Precisely controlling the amount of negative current requires a specialized controller, such as the Texas Instruments UCC28780.

Limiting the nodal capacitance Csw_total to a minimum is also critical. A higher switch-node capacitance requires more negative current, which drives up core loss. Equation 3 shows the main components that contribute to the total capacitance seen at the switch node:

Csw_total = Coss_QH + Coss_QL + CXfmer + CD_Boot + Cossreflected (Equation 3)

where Coss_QH is the clamp FET’s (QH’s) total output capacitance, Coss_QL is the output capacitance of the primary FET (QL), CXfmer is the transformer’s parasitic capacitance, CD_Boot is the boot diode’s parasitic capacitance, and Cossreflected is the reflected output capacitance of the synchronous rectifier FET.

The most critical components in this design tend to be the two primary FETs, so you must give careful consideration while selecting them. With ZVS, most of the loss in the primary FET (QL) will be conduction loss. Thus, RDS(on) becomes the key specification, but remember that as RDS(on) decreases, it does so at the expense of an increased Coss, which drives up the switch-node capacitance. Going for ultra-low on-resistance in QL will not result in an optimal design. A good starting point for 50-W to 100-W active-clamp flyback designs is picking QL with an RDS(on) range of 150-350 mΩ.

A common mistake that designers make is choosing the same FET for both QL and QH. The root-mean-square (RMS) current in QH is lower than in QL, and thus QH can tolerate a higher on-resistance. Figure 3 compares the use of optimized FETs versus using the same FETs for both QL and QH with very low on-resistance. As you can see, you can attain higher efficiency and lower power loss at a much lower cost by optimizing each FET. For even higher efficiency needs, you could reduce Coss further by using gallium nitride FETs instead of silicon FETs, but this increases cost. Figure 3 Optimized FETs are one-third as expensive, yet provide greater efficiency and decreased power loss, as using matched FETs in an active-clamp design.

You can further improve efficiency by reducing the RMS current in QH through a technique called secondary resonance. With primary resonance, the transformer’s leakage inductance resonates with only the clamp capacitor during the transformer’s demagnetization time. As shown in Figure 4, secondary resonance uses a simple inductor-capacitor filter on the output to have the leakage inductance resonate with the added secondary resonant capacitor (Csec_res), such that CClamp >> Csec_res /(primary to secondary turns ratio)2. Figure 4 Additional circuitry creates a secondary resonance with the transformer’s leakage inductance to reduce RMS current in QH.

Figure 5 shows the same circuit with both primary resonance (left) and secondary resonance (right). Both are taken at identical specifications and clearly show how secondary resonance changes the shape of the currents and decreases the primary RMS current. Using secondary resonance results in lower conduction losses in both the primary winding of the transformer and QH. The efficiency improvement is largest at lower input voltages where the primary current is the highest. In many cases, implementing secondary resonance can yield an efficiency improvement of 1% at 90 VAC. Figure 5 Adding the secondary resonance circuit (right) helps reduce primary RMS current. (yellow: VSW; blue: primary current; green: secondary current)

When designed properly, the active-clamp flyback can achieve impressive efficiency and power density. It is critical to use a controller that maintains transition-mode operation with optimal negative current.

The next time you are designing an active-clamp flyback, remember how important it is to optimize FET selection to minimize the switch-node capacitance, and to add a secondary resonance circuit to increase efficiency and thermal performance.

Sarmad Abedin is an applications engineer at Texas Instruments.

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