The tool identifies and fixes traceability gaps between disparate systems like requirements, specs, EDA and software code in SoC designs.
A new tool claims to identify and fix traceability gaps between disparate systems such as requirements, specifications, EDA toolsets, software code, and documentation in system-on-chip (SoC) designs. That allows chip designers to know immediately when a change occurs and its effect on other design artifacts and parts of the system.
Harmony Trace, implemented as an enterprise-level server-based application with a web-based user interface (UI), facilitates complete visibility of requirements traceability throughout the entire SoC design flow and product lifecycle. Moreover, it eases compliance with functional safety and quality standards such as ISO 26262, IEC 61508, ISO 9001, and IATF 16949.
Figure 1 Harmony Trace automates SoC design traceability by interfacing with EDA, documentation, existing requirements, software engineering and support systems. Source: Arteris IP
A complex SoC often involves a suite of disparate and disconnected tools. So, when SoC goes through its product lifecycle, design engineers need to manage the whole lifecycle. “That makes it difficult to trace design requirements and artifacts across the SoC lifecycle,” said Mike Demler, senior analyst at The Linley Group. “Harmony Trace mitigates these issues by connecting discrete silos, enabling users to track requirements, implementation, verification and documentation mismatches across existing systems.”
It also means that SoC designers can continue to use EDA and other tools like IBM DOORS, Jama, Jira, DITA, and IP-XACT. “Harmony Trace establishes automated traceability flow and implements change management among requirements, specification, EDA, code repository, and documentation tools,” said K. Charles Janac, president and CEO of Arteris IP.
The tool shows how Arteris and Magillem technologies have merged to track all SoC requirements and trace them throughout the design process. Arteris acquired Magillem in November 2020 and made it the IP Deployment Division in the company. “Our network-on-chip (NoC) interconnects need information from every IP block attached to it to be able to configure it properly,” said Kurt Shuler, vice president of Marketing at Arteris IP. “Magillem creates that information for each IP block.”
As a result, there is automatic connectivity of IP blocks based on Magillem’s IP-XACT metadata.
Figure 2 Harmony Trace features automatic connectivity of IP blocks based on the IP XACT metadata. Source: Arteris IP
Paul Graykowski, senior technical marketing manager at Artris IP, further elaborated the rationale. “There are a lot of IPs that go into an SoC, and we interconnect them utilizing the NoC technology,” he said. “For that, we need the information relating to these various blocks, and that’s where the Magillem technology comes into place.” The IP-XACT model provides all the configuration information to put the chip together.
We have all this metadata to automate much of the synthesis flow for the topology, Graykowski added. So, engineers can do a lot of optimizations for power, performance and area (PPA), memory management, and software interface control. “That’s how we are going to put everything together while not having to re-input information at every step of the way as we build the SoC.”
Traceability in SoC design
When it comes to SoC design, it all starts with requirements that get translated into architecture. Architects hand it over to the design team, which builds specs and starts implementing that design with coding. The coding is followed by some basic-level tests at the subsystem level, and after that, integration tasks are performed in collaboration with hardware and software teams.
Finally, you end up at the acceptance phase, where high-level checks make sure that the chip has met its goals and documents are released. However, each one of these phases outlined above has its own checks in place. So, if something in verification is discovered, engineers go back to the design board, impacting requirements.
Here comes the rub; design engineers must trace these impacts.
It’s worth mentioning that each one of these phases uses its own toolsets. If you are working with requirements, chances are you are using IBM DOORS. These requirements have to be translated into an actual architecture because tools don’t talk, and then that has to be translated into the design side, starting with HDL coding and running simulations.
But each one of these phases has a gap. So, one person takes the information and translates it into a data source. However, the tools in these phases don’t talk to each other, so you have to tweak all this. And if you miss something in all these gaps, what happens is that when you have silicon in-house, you find out that you have an issue that violates a requirement. As a result, you might have to re-spin the chip, which is very expensive.
Figure 3 Harmony Trace collects, maintains and reports information moving across different SoC building blocks. Source: Arteris IP
“That’s where Harmony Trace comes in, said Graykowski. The tool aims to bring all this together, so if anything changes along the way, SoC designers know immediately that a specific requirement has been violated. “Harmony Trace links all these systems, creating one big system where everything talks to each other,” he added. “There is a complete visibility to anything that changes, and engineers can react to that change in real-time and fix it so that it doesn’t become a costly problem down the road.”
Traceability tool’s key features
When it comes to the unique features of Harmony Trace, the first thing is that while it’s putting things into one system, users don’t have to change their existing flows. They can continue to use tools—such as IBM DOORS and Jira—they are already using. Harmony Trace connects these tools across a single process, filling the gap in these systems. The user logs in through a web browser and can interact with how requirements are linked with artifacts and monitor violations.
So, if something downstream changes and violates the requirements, it gets identified, and then some human interaction can happen to take care of that issue.
Also, the tool has built-in support for industry standards such as ISO 26262, IEC 61508, ISO 9001, and IATF 16949. That, among other things, accelerates functional safety assessments by identifying and fixing the traceability gaps between disparate systems.
Another thing that Harmony Trace offers is built-in reporting. Right now, engineers are doing their engineering work while they also track things and create reports, which are either used for design review or certification and safety audits. “That’s a lot of time and effort, and it’s not always done in the same way,” Graykowski noted.
He added that with Harmony Trace, all the information moving between different systems is collected, maintained, and reported. Design engineers can get the report with a click, take that report and work with their peers on design reviews or safety audits. That makes their life much easier.
More traceability features
Harmony Trace captures design history, and all that information is stored in the tool and can be easily output. The tool offers four to five report types, and they are available in PDF, Word, and Excel formats. A multi-page report usually comprises 38 to 40 pages.
Then there is traceability matrix, a spreadsheet that is color-coded; on one access, there are all requirements, and on the other access, it has all the artifacts for the requirements. The matrix shows how they are linked and if they are linked. Harmony Trace also has a built-in API that enables engineers to customize the report. They can tweak it as well if they need it in a particular format.
“The number one benefit of Harmony Trace is that every requirement is tracked and downstream modifications are identified,” Graykowski concluded. “When they change and violate the requirement, a review process is triggered.”
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