Reaping the benefits of instant-on FPGAs

Article By : Ted Marena, Microsemi

Instant-on devices can operate in the early points of the system voltage’s power-up curve and serve a vital function in supporting complex power-on sequences, self-test at startup, and more. But what does it mean for a device to be instant-on?.

A system is composed of multiple components with various interdependencies and numerous voltages and interfaces, and the designer’s task is to make sure all these elements work together. This can be as simple as ensuring that power supplies are sequenced correctly, but this is often just the starting point. Some boards require that a self-test be performed at startup. Processors may need to be held in reset until an SRAM field programmable gate array (FPGA) is loaded or power rails reach appropriate levels. Therefore, it is vital to choose instant-on devices for the system’s critical paths in order to achieve proper initialization and system operation.

But what does it mean for a device to be instant-on? As the following illustration shows, instant-on devices are operational before the system voltage has reached its minimum level, which is defined as the power-up stage. This contrasts with devices that are operational only after power-up.

Figure 1: Instant-On Devices Power Operation (Source: Microsemi)

Semiconductors that can operate in the early points of the system voltage’s power-up curve are considered to be instant-on. Some architectures, such as smartphones and PCs, are very structured, with dedicated devices to support the system initialization, but these fixed system-initialization devices are not adequate for the majority of embedded designs. Although some sequencing and monitoring devices could be used, there are typically many other functions that must be supported. Consequently, many designers choose to use large complex programmable logic devices (CPLDs) or small FPGAs that are instant-on.

From the 1990s through the mid-2000s, CPLDs were a mainstay in numerous embedded boards. The configuration of these devices was directly controlled by electrically erasable complementary metal oxide semiconductor (EECMOS) or flash cells for all the logic in the devices. These directly-controlled cells allowed the device to power up instantly—often on the order of hundreds of microseconds. When a device is ready in less than a millisecond, designers can reliably count on the ability to initialize a system, control supplies, keep processors in reset, and so on. CPLDs were broadly used, mainly due to this instant-on capability.

By the mid-2000s, no additional CPLD devices were being developed, and the focus moved to small FPGAs that were more cost-effective and feature-rich than CPLD, easily replacing the older devices. The new generation of small FPGAs were purported to be instant-on, and featured two different types of architectures. One was similar to CPLDs in that it used flash to directly control the logic configuration, meaning that the flash cell directly configured the logic elements and enabled a device power-up time much less than a millisecond. The other architecture was a hybrid, sometimes referred to as “flash on the side.” This was actually a SRAM device that also incorporated flash.

In general, flash-based FPGAs offer a variety of advantages over SRAM-based FPGAS, and this is particularly true for designs requiring instant-on, even when an SRAM FPGA has been enhanced with flash-on-the-side capability. “Flash on the side” devices initialize the SRAM portion of the FPGA as power is applied, which leads to near instant-on times but, because of the need to load the SRAM, the startup is in the several-milliseconds range (depending on the density). These devices enable a capability that is sometimes referred to as “live after power up.” For some designs, these hybrid devices can be used to initialize a board, but additional care must be taken if these parts are used.

For designs that need true instant-on capability, an FPGA must have a flash cell that directly configures logic elements. Only flash-based FPGAs can be used to drive down total system costs by eliminating the need for additional power-up and initialization circuitry. In many systems, they are the only devices that can assist in system startup tasks, system configuration, and supervision during voltage ramp-up, which can result in total system cost savings.

In addition, certain battery-powered applications can benefit greatly from the instant-on capabilities of flash-based FPGAs because they power up and down more quickly and do not have the same spike in rush current or initialization current that flash-on-the-side SRAM FPGAs consume. Another benefit of the flash-based FPGAs is that they are immune to single event upset (SEU) configuration changes. In contrast, all SRAM FPGAs (including flash-on-the-side hybrids) are susceptible to particles in the atmosphere that could flip their value from a 1 to a 0 or a 0 to a 1. This could affect the logic design and cause unintended functionalities or a complete system failure. These many advantages of flash-based FPGAs over SRAM-based alternatives make them optimal solutions for safety-critical, industrial, automotive, medical, military, and other applications that require immediate operation, as well as lowering the total system cost.

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Understanding Power-Up Stage Classifications

The power-up stage is often broken into three categories: instant on (level 0), live after power up (level 1), and live after power stable and system initiated (level 2). In level 0, devices are operational between power-on and power-up (the time at which the applied voltage has reached the lower limit of system voltage and is stable). Devices such as ASICs, some ASSPs, and flash-based FPGAs from Microsemi fit into the level 0 category. Level 1 devices require a configuration download from internal memory, but are operational before system initialization; devices in this category include ASSPs and flash-on-the-side FPGAs, like those from Altera and Lattice. Level 2 devices are operational only after the initialization of system clocks, resets, interfaces, and memories, and include most SRAM-based FPGAs and processors.

Table 1: Power-up Stage Classification (Source: Microsemi)

This classification system helps designers choose the appropriate programmable logic devices for their applications, taking into account the operation and functionality during system power-up stages.

FPGAs based on volatile SRAM make system startup complex and expensive due to their need to load configuration data from internal or external memory before they are operational. In contrast, instant-on FPGAs simplify application startup, reduce total system cost, PCB size, and power consumption, and also increase system reliability and security. These instant-on FPGAs can implement the same functions as SRAM FPGAs, but simplify the design because they perform all the initialization functions and implement all the logic required on the board. These flash devices eliminate engineers’ concerns over whether power-up time will be an issue, as is the case with flash-on-the side FPGAs. The latter also consume more power, are susceptible to SEU failures, and take much longer to power up than true instant-on flash-based FPGAs. These SRAM FPGA shortcomings may require the designer to use additional components or make other system compromises.

The following table provides a comparison of the two architectures at similar densities.

Table 2: Power-up Timing: Flash-based versus Flash-on-the-side and SRAM-based FPGAs (Source: Microsemi)

Instant-on FPGAs eliminate concerns about board initialization and power-up sequencing by delivering truly instant-on startup time. Flash-based FPGAs are up and running before anything else must be controlled. This simplifies designs and reduces bill of materials (BOM) costs by eliminating the need for additional components. Flash-based instant-on FPGAs solve the challenges of designing systems that require these start-up capabilities, while also enabling traditional FPGA functionality. The benefits of instant-on functionality—lower power consumption, SEU immunity, and additional integration capabilities—are crucial for a broad class of designs.

Ted Marena is the director of FPGA/SOC marketing at Microsemi. He has over 20 years’ experience in FPGAs. Previously Marena has held roles in business development, product & strategic marketing.

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