Making a reset usage strategy in ASIC/FPGA designs

Article By : Mufaddal Saifee, Jaymin Patel

The need for reset is governed by the system design and application, and various data and control paths are designed to use a reset signal.

Reset is an important mechanism to bring a digital system into a known state. The need for reset is governed by the system design and application, and various data and control paths are designed to use a reset signal. Flip-flops in the control path should have reset parameters to bring the system to a known state, while one can usually do without reset in the data path. Let’s discuss various use cases of resets in ASICs and FPGAs.


Various data path systems are designed to synchronise with inputs, process them and provide output. For such designs, if all the unused states are waiting for acquiring the sync state, then the design can do without ever being reset. For designs where the state machine logic has been optimised during synthesis by avoiding logic reduction, resets are a must to prevent the design from starting in a random state.

There are various scenarios apart from the device reboot where the resets are required in real-world designs. Some likely scenarios include:

  • If a clock source drops out, then the design should enter the reset until PLL lock is acquired.
  • Communication channel must be reset, when the link partner loses sync.
  • A user-accessible push button reset.
  • Reset from microprocessor after some event, example after expiry of a watch dog timer.
  • Partial reconfiguration in modern FPGAs where the swapped logic block must be reset independently of its environment.
  • Use of legacy IP from previous ASICs or an IP vendor requiring reset.
  • Reset to start clean simulations.

To achieve better performance, designs nowadays have their data pipelined through chains of flip-flops. For such designs, the usage of reset can be eliminated in the pipelined Flops to achieve better area utilisation and performance. Choosing reset usage and its strategies in ASIC/FPGA designs require many design considerations like whether every flip-flop will require a reset, whether to use a synchronous reset or asynchronous reset, how the reset tree will be structured and buffered, how to verify timing of reset tree, how test scan vectors are applied to check functionality of reset and how reset is handled in multi clock domain designs. In this article, we will see the reset usage in Data and Control path in ASIC and FPGA. We will also see how FPGA components like shift registers, Block RAM, Distributed RAM, and DSP Slices can be used efficiently with proper use of reset.

Reset usage in data & control paths in ASIC

A common belief with most designers is that all the flops in the design should be having a reset. This is not true for data paths. flip-flops in control path do need a reset but flip-flops in data path can go without it. All these pipelining flip-flops or delay flip-flops don’t need resets. Moreover shift registers, data bus etc. which depend on some resets, to indicate valid data at any time can do without a reset signals.

For a design having a pipelined or delay chain, flip-flops with synchronous resets as shown in below Figure 1 can be implemented with a single resettable input flip-Flop as shown in Figure 2. The only thing to be taken care of by the design shown in Figure 2 is that it should held the synchronous reset asserted for duration long enough to flush the entire pipeline.

__Figure 1:__ *Pipeline follower flip-flops with synchronous reset signal in data path*

__Figure 2:__ *Pipeline follower flip-flops without synchronous reset signal in data path*

For the designs where the validity of data is indicated by a valid signal, we can remove reset signal in data-bus path and only provide reset to the valid signal generating flip-flop as shown in Figure 3.

As we can see that the reset signal is not present in the data path and valid data is latched whenever the load signal is asserted. Once, data is captured on load signal, then it can be shifted freely in the pipeline. The control signal is also delayed with data path to synchronise the last stage flip-flop output.

__Figure 3:__ *Pipeline flip-flops with synchronous reset signal in control path*

Eliminating the need for reset signal in data path will reduce the total number of resettable flip-flops required in design and thus, reduce the overall number of gate counts. The benefits of using flip-flops without reset are,

  • Reduced logic utilisation
  • Lesser routing challenge
  • Thus lower routing run time
  • Better timing performance.

The golden rule for minimal reset design is that all registers that receive state through feedback must be reset. Generally reset is needed in following conditions.

  • Flip-flops within a feedback loop
  • Flip-flops holding the state of the state machine
  • IIR filter flip-flops

Next: Coding consideration for pipeline flip-flops

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