As data rates have gone above 10 Gbps, the adequacy of redrivers has abated across many applications, and retimers are becoming the signal conditioner of choice.
Digital retimers came to prominence in the 1960s with the emergence of the telecom digital carrier systems: T1 and E1. These systems carried multiple channels of voice circuits over a shielded twisted pair with a digital retimer installed every few thousand feet. They were advanced in their day and used similar technologies to what are used in today’s high-speed retimers, including equalization, clock-data recovery (CDR), line coding, and framing.
For every serializer/deserializer (SerDes) use case, there is always an additional application that needs enhanced reach. Typical applications for redriver or retimer chips are to:
Redriver and retimer comparison
A typical redriver datapath includes a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), and a linear driver. The CTLE is used to equalize the frequency dependent loss experienced in the channel. The VGA is used to restore the amplitude of the signal. The linear driver is used to drive the channel at the correct impedance.
Redrivers often have input loss-of-signal threshold and output receiver (Rx) detection capability, and a squelch detector that differentially detects the presence of a communication signal on low-speed channels. Figure 1 illustrates a typical redriver block diagram.
Figure 1 This block diagram of a typical redriver shows a CTLE to equalize the frequency dependent loss in the channel, a VGA to restore the signal’s amplitude, and a linear driver to drive the channel at the correct impedance.
Analog redriver limitations
The three main disadvantages of an analog redriver are:
As a result, the full reach of the link both before and after the redriver cannot be utilized. Shorter trace lengths must be employed in each place to minimize the impact of the added noise, residual ISI, and narrowed eye width. Due to these issues, a significant burden is placed on the system developer to understand and characterize the complex impact of the redriver on the end system across all envisaged usage scenarios.
For additional insights on the types of channel impairments that degrade signal integrity, and the roles that redrivers and retimers play in correcting them, see Preserve signal integrity with Ethernet retimers and redrivers.
How retimer works
A typical retimer is a mixed-signal analog/digital device that is protocol aware and has the ability to extract the embedded clock, fully recover the data, and retransmit a fresh copy of the data using a clean clock. In addition to the CTLE, VGA, and driver stages, also found in a redriver, a retimer contains a CDR circuit, a long-tail equalizer (LTE), and a decision feedback equalizer (DFE).
The LTE compensates for long-term impulse response impairments, and the DFE acts as a nonlinear equalizer, suppressing the ISI due to channel imperfections such as high-frequency losses and notches.
Internal digital logic, state machines, and/or a microcontroller manage the automatic adaptation of the CTLE, VGA, LTE, and DFE blocks, and implement the protocol link training and status updates. Figure 2 illustrates a typical retimer block diagram.
Figure 2 Beside CTLE, VGA, and driver stages also found in a redriver, a typical retimer includes a CDR circuit, LTE, and DFE.
In simple terms, a redriver just amplifies a signal, whereas a retimer fully recovers the data and sends out a crisp new copy. Figure 3 illustrates this and shows how an attenuated eye opening is boosted by a redriver and completely regenerated by a retimer.
Figure 3 Three examples—the eye attenuated by a channel (left), the eye after a redriver (middle), and the eye after a retimer (right)—illustrate how a signal is boosted by a redriver and regenerated by a retimer.
In order to accomplish its goal, a retimer has to be protocol aware. Retimers snoop the link configuration transactions that pass through it and set themselves up in the right modes. In some cases, retimers also participate in the link setup operations. Because of these automated steps, manual tuning for specific channels, cables, and form-factors is not required, making system integration at higher data rates much simpler.
Retimers for high-speed specifications
A number of high-speed and hard-to-implement SerDes specifications have been recently released, including those contained in USB4, PCIe 5.0, CEI-28G, and CEI-56G, along with the PCI 6.0 and CEI-112G specifications that are still under-development. All of these new standards are aimed at addressing the demand for ever-higher data throughput.
Eight generations of SerDes and their pre-cursors have emerged over 20 years from the combination of the Optical Internetworking Forum (OIF) and IEEE 802.3 Ethernet committees. With each generation, vendors have developed bit-level, protocol-agnostic retimer products to enable system makers to reach further.
These SerDes and corresponding retimers have been used, adapted, or influenced systems extensively in telecom, Ethernet, Interlaken, RapidIO, serial advanced technology attachment (SATA), serial attached (SCSI) SAS, fibre channel, InfiniBand, and numerous proprietary systems. Redriver chips were never popular in the OIF/Ethernet family of ecosystems due to the typically more tightly-engineered links, which use up the link margin.
PCI express (PCIe) is a high-speed serial computer expansion bus standard. It is the standard motherboard interface for personal computer graphics cards, hard drives, SSDs, Wi-Fi, and Ethernet hardware connection. The PCIe 3.0 specification, running with 8 Gbps lanes was well served by redrivers. PCIe 4.0 doubled the speed to 16 Gbps lanes, and redrivers struggled to solve the problem and delivered modest benefits to system implementers.
In May 2019, the PCI-SIG standards body officially released the specification for PCIe 5.0 with data lanes running up to 32 Gbps. Though the increase in speed combined with the need for increased expansion capabilities, the end of the road for PCIe redrivers seems near. As we move forward to the coming PCIe 6.0 standard, the fragility of PAM4 makes even the consideration of redrivers a non-starter.
Then there is universal serial bus (USB), an industry standard for interfacing between computers, peripherals, and other computers. USB 1.0 was released in 1996, followed by USB 2.0 in 2000. Even though redrivers were not standardized by the USB-IF, the benefits they provided in terms of reach extension and voltage compatibility made them indispensable.
With the release of USB 3.0 in 2010, signal integrity challenges in USB became more pronounced and enhanced redriver products came to the market to extend the reach of the Superspeed 5 Gbps links. This trend continued with USB 3.1 and Superspeed+ 10 Gbps links. The USB 3.2 specification extended the single lane modes in USB 3.0 to dual lanes over the USB-C connector and further increased the number of applications for redrivers.
In August 2019, the USB-IF officially released the specification of USB4 that enhanced the performance of the links even further to 20 Gbps lanes (40 Gbps links over 2 lanes). The 20 Gbps signal is much more fragile than its predecessors, making it more vulnerable to ISI, passband ripple, jitter sources, analog mismatches, termination mismatches, intra-pair skew, reflections, thermal noise, and power supply noise. As a result, the era of redrivers for USB is coming to a close.
The newer high-speed interconnect specifications will drive a new generation of signal conditioning solutions. Digital retimers are key elements for maintaining signal integrity while sending very-high-speed data over challenging channels. At rates above 10 Gbps, there are many challenges to using a redriver. This is a core reason why retimer support is being anticipated and has been written into recent specifications.
In summary, signal conditioning technologies such as redrivers and retimers are useful in many system environments. As data rates have gone above 10 Gbps, the adequacy of redrivers has abated across many applications. In the OIF/Ethernet ecosystems, retimers have been the signal conditioner of choice. In the PCIe ecosystem, PCI 4.0 is the last gasp for redrivers, with retimers delivering a better solution. In the USB ecosystem, USB4 is the transition point where redrivers have become the wrong answer to the system problem.
Protocol-aware retimer solutions offer the necessary signal integrity performance for USB4 applications, and offer a robust, no-excuse development path and a cost-effective system solution to meet consumer demand.
This article was originally published on EDN.
Brian Holden is vice president of standards at Kandou.
Paul Wilson is director of product marketing at Kandou.