The PCB is now so fundamental that we often forget that it is a component that must be selected based on its specifications to deliver the required performance.
Satellite and spacecraft avionics are increasingly combining K-band RF, high pin-count, ultra deep-submicron GHz-speed digital, GSPS analogue, and low-voltage, high-current power distribution onto a single PCB. All of these distinct functions place unique requirements on the design, layout, and construction of a PCB, the selection of a suitable dielectric material, the number of layers in the stack-up and their allocation, floor-planning, the size and shape of power/ground planes, component placement, routing, trace geometry, and grounding strategy.
Innovations are increasingly occurring at a physical board level, e.g. low-inductance interplane capacitance, embedded passives, and planar antenna structures. The performance of many space-electronics sub-systems is dependent on the physical realisation and implementation of the design; the PCB is now so fundamental that we often forget that it is a component and like all parts, must be selected based on its specifications to deliver the required performance!
With so much emphasis on time-to-market, I have decided to write a series of articles on right-first-time PCB layout for spacecraft avionics.
You have just completed schematic entry, pre-layout analyses to verify signal integrity and optimise the PDN, packaged your design, and all of those unassigned reference designators get allocated real values. The project is forward-annotated and then a blank layout appears. What should you do next to physically realise your design to build your prototype or product?
Typically the next steps are to draw the board shape and routing borders, define the number of layers within the stack-up and their allocation, e.g. routing or plane, horizontal or vertical tracks, analogue, digital or power. Via types and spans, as well as pad geometries, are then defined from the manufacturing capability of your fabricator, plane shapes are constructed and assigned to the appropriate supply or return nets, and the width of controlled-impedance traces are calculated based on the dielectric permittivity, track thickness, and clearance. Components and connectors are then placed onto the blank layout before beginning routing. With so much pressure on time-to-market, should you manually route or can you trust automated methods? Powerful, semi-automatic techniques such as sketch and hug routing allow many nets to be laid quickly and intelligently, requiring minimal human instruction.
As the performance of PCBs continues to increase, the selection of the dielectric has become more important to ensure your designs are fabricated right-first-time. An increased number of exotic materials are being qualified and used for the core and pre-preg to minimise loss at higher frequencies and edge rates.
In terms of impedance planning to avoid reflections on transmission lines, there are many free online calculators and expensive field-solving tools that calculate the required trace width. My favourite is In-Circuit Design’s excellent stack-up planner, which you can evaluate free for fourteen days. It allows you to quickly create a virtual stack containing the required number of layers and then you can experiment with dielectric materials to optimise the characteristic impedance by adjusting permittivity, trace width, clearance, thickness, and separation for differential pairs (see the YouTube tutorial video below). The resulting stack can be imported directly into Mentor Graphics’ Expedition flow.
With today’s large pin-count, space-grade FPGAs, optimising the routing between devices to minimise crossovers (layer changes) and the number of layers can be a challenge. Tools such as Mentor Graphics’ IO Optimizer have automated this process, simplifying routing effort and PCB design.
To minimise costs, PCBs are increasingly being used as the heat sink, so understanding the current-carrying capacity of traces and planes and their resultant voltage drops are important to ensure your designs are fabricated right-first-time thermally. As an example, you are using a 1 V, 20 A space-grade FPGA; how do you manage the distribution of heat? There are many free online calculators reporting different results and the original IPC-2221 standard is outdated. Recent research has added to our knowledge of temperature rise and power drops, complemented by EDA advances in post-layout power integrity.
Some suppliers of space-grade semiconductors are considering smaller pitches: this uniquely impacts the space industry as we have access to a limited set of qualified PCB dielectrics resulting in wider traces. The routing of 50 and 100 Ω transmission lines becomes very difficult when the pitch is reduced to less than 1 mm. Concomitant with this need, anything other than via-in-pad technology can result in parastic inductances that impact the effectiveness of the PDN.
Next time, we will discuss stack-up planning: what criteria to consider when selecting the number of layers and the resulting implications for routing, grounding, EMC, and fabrication cost. I will provide a set of guidelines which you can use as a checklist to ensure future designs are right-first-time. Future posts will include re-using schematics and layouts for different projects/customers to meet their time-to-market needs.
Meeting time-to-market requirements and/or the needs of financial investors, creates huge pressure on satellite and spacecraft OEMs to get their products out there quickly. Spacechips now teaches a one-day training course on Right-First-Time PCB Design and Layout for Spacecraft Avionics. Module 1 covers stack-up planning and dielectric material selection, while Module 2 discusses forward annotating the schematic to layout, floor-planning, component placement, and creating and assigning planes. Importing or creating part footprints are also taught as our industry starts using more and more esoteric packages. Better communication between EDA companies, component vendors and spacecraft manufacturers is required to ensure schematic symbols, footprints, and 3D models are readily available.
Module 3 covers the routing of transmission lines; how to calculate the current-carrying capacity of traces and planes; the use of constraints; and how to layout RF, GHz digital, GSPS mixed-signal, switching DC-DCs, and low-voltage, high-current designs. I peer review many regulator designs that have perfect schematics, but the layout is incorrect resulting in noisy supply rails, low efficiency, and poor transient response. Module 4 discusses specific manufacturing challenges for the space industry, such as ESA vs. IPC standards, using silkscreen or soldermask without out-gassing, and whether the formal standards can be used to reliably sign-off the latest designs before sending them to the fabricator. Real examples are demonstrated using Mentor’s Expedition flow to reinforce the learning. Contact us for further information.
Until next month, the first person to tell me why solder mask can be problematic for large pin-count space-grade semiconductors will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to George from San Jose, USA, the first to answer the riddle from my previous post.
Spacechips will be teaching its three-day course on Space Electronics in Sydney and Adelaide, Australia this April and in Rome, Italy this May.
Dr. Rajan Bedi is the CEO and founder of Spacechips, which provides ultra high-throughput on-board processing and transponder products, design consultancy in space electronics, training, technical-marketing and business-intelligence services. You can also contact Rajan on Twitter.