RISC-V Foundation clears up Princeton’s ‘100 errors’

Article By : Peter Clarke

A single change to the RISC-V instruction set architecture specification may eliminate the failures, according to the foundation.

The RISC-V Foundation has set the record straight on reports that Prince University researchers found more than 100 errors with memory consistency model in more complex implementations of the open source RISC-V.

The RISC-V project is seeks to facilitate open-source design for computer chips, offering the possibility of opening chip designs beyond the few firms that dominate the space. However, a team of Princeton researchers put out a report several weeks ago, in which they said they have discovered errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture.

Now, the foundation has finally commented on the report. In an article published at the RISC-V Foundation's website, Chairman Krste Asanović pointed out that although a particular RISC-V design failed over 100 tests, with reference to the C11 high-level programming language, a single change to the RISC-V instruction set architecture (ISA) specification could eliminate all these failures.

The article stresses that the unmodified Rocket core did not exhibit any illegal behaviour because it does not reorder memory accesses aggressively. The problematic behaviour occurs when additional re-ordering is done that would be legal under the current version of RISC-V.

"It is important to note that a failed litmus test does not correspond one-to-one with errors in the MCM, as a single change in the MCM could remove all litmus test failures," Asanović wrote in the blog post.

The RISC-V Foundation is the not-for-profit body set up to administer the RISC-V open-source ISA. RISC-V is becoming a standard open architecture for industry implementations with backing from numerous companies including AMD, Google, Hewlett Packard, Huawei, IBM, Micron, Microsemi, Microsoft, Nvidia, NXP, Rambus, Qualcomm, Samsung and Western Digital. The technology, if widely adopted, could be disruptive to the business models of established IP licensors such as ARM and Imagination.

There is no conflict between the two parties. Asanović noted that the RISC-V Foundation has been working with the Princeton team since December 2015, as well as with other memory consistency model (MCM) experts, to help tighten up the RISC-V ISA specification to avoid these problems. This work is part of converting the original Berkeley-authored RISC-V specifications into an ISA standard that will be ratified by the RISC-V Foundation. This process is expected to complete in 2017.

The intention is for the MCM changes in the spec to be backwards compatible, such that existing simpler cores would run code written to the new specs correctly.

Asanović went on to say that the Princeton team had also reported on the use of their tools TriCheck and PipeCheck, on proprietary ISAs and shown them to have unresolved bugs in shipping products.

"We note that no proprietary ISA vendor has published a formal memory model that they guarantee their products will obey," said Asanović.

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