Samsung Foundry adopts Synopsys and Ansys co-developed solution for advanced-node, energy-efficient chips

Article By : Synopsys Inc.

Samsung Foundry has achieved high silicon correlation with the jointly developed solution built on Synopsys PrimeTime signoff technology and Ansys RedHawk-SC.

Synopsys Inc.’s advanced voltage-timing signoff solution developed in collaboration with Ansys has been adopted by Samsung Foundry to accelerate the development of its energy efficient designs with optimal power, performance and area (PPA). The offering is built on golden-signoff products, including the Synopsys PrimeTime static timing analysis, Synopsys PrimeShield design robustness, Synopsys Tweaker ECO and Ansys RedHawk-SC digital power integrity signoff solutions, and delivers the industry’s highest accuracy and throughput, savings weeks of time.

Samsung Foundry has reported high silicon correlation using the integrated solution. “Dynamic voltage-drop and power integrity are significant challenges for energy efficient design,” said Sangyun Kim, vice president of Design Technology at Samsung Foundry. “The new Synopsys-Ansys voltage-timing solution shows good correlation with silicon and is especially effective in accurately estimating DVD impact on bus-pipeline paths. Samsung Foundry plans to deploy the solution on production designs at advanced nodes to prevent failures in silicon and maximize design energy efficiency.”

At advanced nodes, DVD and power integrity become even more challenging, with the potential for increased variability and greater difficulties in achieving accurate delay calculations. However, inaccurate timing assessment of DVD violations can result in missed DVD-related timing silicon failures. Some design teams utilize pessimistic guard-bands and margins as a work-around, but this approach can lead to over-design, sub-optimal energy efficiency and PPA, as well as protracted design closure iterations. The new solution catches real design and silicon bugs that traditional, disjointed flows can miss, preventing over-fixing by minimizing DVD and timing pessimism.

“Building on our long-standing collaboration to enhance design implementation, we’re pleased to extend our efforts to the signoff realm,” said John Lee, vice president and general manager of the Electronics and Semiconductor Business Unit at Ansys. “With our RedHawk-SC technology along with PrimeTime static timing analysis solution, Ansys and Synopsys are the only two companies that can address signoff fidelity, silicon correlation and throughput at advanced nodes, accelerating time-to-market and quality-of-results.”

The PrimeTime and PrimeShield solutions identify DVD-sensitive critical paths, sharing this data with RedHawk-SC, which generates critical path-aware directed scenarios and vectors to perform accurate DVD analysis. The RedHawk-SC solution also provides high-fidelity, instance-specific piecewise-linear VDD and VSS waveforms to the PrimeTime solution, which employs its advanced waveform propagation engine to compute highly accurate timing impact insights.

“Working closely with Ansys, we’ve solved one of the industry’s toughest timing signoff-related challenges, enabling designers to reduce iterations and achieve their energy-efficiency and PPA targets weeks earlier,” said Shankar Krishnamoorthy, general manager and corporate staff for the Silicon Realization Group at Synopsys. “Our PrimeTime solution has demonstrated 3% correlation to HSPICE, the most accurate in the industry, while the cloud-based architecture of RedHawk-SC delivers the speed and capacity for full-chip analysis. From our earlier work integrating RedHawk Analysis Fusion with our IC Compiler™ II place and route solution and Fusion Compiler RTL-to-GDSII solutions, we’re continuing to empower designers to meet their tough power integrity requirements and realize better PPA outcomes.”


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