TechInsights discusses which wafer bonding technology hints at a possible future for stacked dies.
Figure 5 is a SEM cross section through a portion of the SONY CMOS image sensor and its underlying control ASIC. The image sensor die is mounted upside down with its top surface wafer bonded to the ASIC. The metal 6 interconnects on the image sensor are seen joined to the metal 8 interconnects of the ASIC. This is the first time that we have seen this form of wafer bonding being used in a commercial CMOS image sensor, and some digging through press releases reveals that Ziptronix had licensed its direct bonding technology (DBI) to Sony in early 2015. Sony had previously licensed Ziptronix’s ZiBond technology in 2011, with this technology likely being used for its earlier backside CMOS image sensors employing through silicon vias (TSVs) to join the image sensor die to the ASIC.
__Figure 5:__ *Sony IMX260 Cross Section (Source: TechInsights)*
__Figure 6 __is a higher magnification SEM cross-sectional image showing the wafer bonding between the image sensor die and the control ASIC. The top surfaces of the two dies have been planarised by chemical-mechanical polishing (CMP) to form the flat surfaces needed to join the two wafers. Ziptronix’s US patent 6,902,987 (‘987 patent) suggests that the surface roughness of the two wafers needs to be less than 3nm RMS and preferably as smooth as 0.1 m RMS.
Simply joining the two wafers together will allow Van der Waal forces (hydrogen bonding) to hold the wafers together, but this bond strength is insufficient for the task. High temperature anneals can convert these bonds to covalent bonding, but high temperature anneals can cause problems with thermal mismatches between the materials making up the two wafers. This is where Ziptronix’s 7,109,092 (‘092) patent comes into play. This patent describes a method for subjecting the wafer’s oxide surface with a fluorinating treatment to promote the covalent bonding of the two wafers in a room temperature process.
This wafer bonding process is likely done prior to the backside thinning of the image sensor wafer that might be about 150µm thick, as is the control ASIC. The two wafers would brought into alignment using IR microscopes to see through the wafers to their respective alignment marks. This process has yielded a misalignment of the image sensor’s metal 6 pad and the control ASICs metal 8 pad of less than 0.25µm.
A CMP process would then be used to thin the image sensor die after the wafer bonding, followed by the back-end processing for the deep trench isolation between the pixels, backside metallisation microlenses and color filters.
__Figure 6:__ *Sony IMX260 Wafer Bonding Surfaces (Source: TechInsights)*
Samsung uses arrays of through silicon vias to connect its S5k2L1SX image sensor to its underlying ASIC. Figure 7 shows a series of Through Silicon Vias (TSVs) arranged on an approximately 5µm x 8µm grid pattern. The TSVs are the dark oval shapes seen at the center of each grid point.
__Figure 7:__ *Top Surface of Samsung S5k2L1SX Image Sensor with TSV Array (Source: TechInsights)*
Figure 8 is a SEM cross section through a pair of these TSVs that penetrate through the entire CMOS image sensor die and the control ASIC’s passivation layer to land on the metal 7 traces.
Like the Sony CMOS images sensor, the Samsung image sensor die and its control ASIC have both undergone CMP planarisation prior to being joined together. But the delamination seen between the two Samsung dies suggests that they are not joined using the same wafer bonding technology used by Sony.
The TSVs connecting the image sensor die to the metal 7 traces of the control ASIC was formed after the two dies are affixed to each other, and after the image sensor die had undergone its backside thinning, using a TSV last process. The TSV metallisation appears to be tungsten with probably a titanium nitride barrier and possibly titanium adhesion layers.
__Figure 8:__ *Samsung S5k2L1SX Image Sensor TSVs (Source: TechInsights)*
Using TSVs to electrically connect the image sensor die to the ASIC certainly gets the job done, but at the cost of the added real estate needed for the TSV arrays. In my opinion, Sony’s direct wafer bonding is the better solution.
Sony’s direct wafer bonding hints at a possible future for stacked dies. And here we look to the Sony IMX240 12 megapixel backside illuminated CMOS image sensor used in Apple’s iPhone 6s. The IMX240 uses copper vias formed as a via-last process to join the image sensor die to the control ASIC, as shown in Figure 9. The top surfaces of these vias have undergone a CMP planarisation process and we think that they could be prepared to accept direct wafer bonding to another die.
__Figure 9:__ *Sony IMX240 Cross Section (Source: TechInsights)*
The randomly distributed bad DRAM and NAND Flash dies on a wafer (yield losses) might make direct wafer bonding an unattractive process for stacked DRAM and NAND products. But we can speculate that this process could be adopted for die-to-die bonding. So does Sony’s direct wafer bonding seen in the IMX260, and its copper via-last process used in the IMX240, give a path for stacked DRAM or NAND dies? It is an intriguing thought.