Satellite avionics grounding and design for EMC

Article By : Rajan Bedi

Many manufacturers of satellite sub-systems don't have a grounding or design-for-EMC strategy to reduce EMI emissions and sensitivity to external RFI.

As on-board processing becomes more sophisticated integrating K-band RF, GSPS ADCs/DACs, and GHz-speed FPGAs on a single PCB, questions often arise about satellite grounding, particularly mixed-signal sub-systems with separate analogue and digital planes, and limiting EMI emissions and susceptibility to external RFI.

Many manufacturers of satellite/spacecraft sub-systems don’t have a grounding or design-for-EMC strategy. Some OEMs adopt a ‘sticking-plaster’ approach during the commissioning of their avionics hardware; the problem with this is that it requires considerable recurring engineering effort and expense, and possibly additional parts, which may have to be manually fitted to provide a non-ideal fix. In this post, I will introduce grounding, routing, and layout techniques that you can use to maximise performance and minimise EMI emissions and susceptibility to external RFI to ensure your designs are right-first-time without incurring additional component costs.

Firstly, ground is always assumed to be zero potential with no resistance or inductance at all frequencies, however, this is simply not the case for high-speed designs and there will always be some impedance, even in a heavy, copper ground plane with large cross-sectional area. By definition, a changing return current flowing through a conductor in a loop creates self inductance, and this, together with the intrinsic sheet resistance of a ground plane, generates a voltage drop whose amplitude increases with frequency and the magnitude of the current. This contradicts the intention of ground being a zero reference, and the voltage potentials across the plane, also known as ground bounce, can produce common-mode currents on external cables which radiate EMI.

To add to the confusion, an avionics sub-system contains a number of different grounds, e.g. signal return, power return, and chassis reference. A circuit may also contain distinct grounds (analogue and digital), and these need to be carefully managed to deliver the required performance by ensuring that noisy logic does not interfere with sensitive analogue sub-circuits, e.g. partitioning and routing discipline. CMOS for example is a saturating logic family with rising and falling transitions generating large transient currents on the power supply and ground planes. Furthermore, rectangular waveforms and fast edges contain high-frequency harmonics that interact with the unwanted impedance of ground planes producing simultaneous switching noise.

As an example, consider a small 1U PCB with a ground plane measuring 95×95 mm with 1 oz copper thickness: the sheet resistance across this copper layer can be approximated using the following equation, R = ρ/H * L/W, to be 0.48 mΩ per unit square, where ρ is the bulk resistivity of the conductor (1.724E-6 Ω-cm) and L, W, and H are the length, width, and thickness of the plane respectively.

diagram of ground plane dimensionsFigure 1 Ground plane sheet resistance can be approximated using its dimensions.

The resistance of the plane and hence its voltage drop can be reduced by increasing either the width or the thickness of the ground layer. For this example, the resistive loss is approximately 0.05 mΩ/cm, which gets larger with frequency due to skin depth, changing the current distribution through the conductor.

The sheet inductance of the above plane can be approximated using the following equation to be 0.027 μH:

equation for calculating sheet inductance

where height and width are specified in mm and length in cm. The inductance of the copper plane can be reduced by increasing either its width or the thickness. The resulting impedance increases linearly with frequency and its voltage drop can be reduced by lowering either the switching rate or the rise time of the forward signal, however, this may not be an option for timing-critical designs. For the above example, the inductive loss is approximately 0.0028 μH/cm.

In geometrical terms, ground planes have the least resistance and inductance acting as a low-impedance reference for high-frequency circuits. They also minimise RFI emissions and because of their shielding action, reduce susceptibility to external EMI. Dedicated return planes also enable high-speed signals to be transmitted as controlled-impedance transmission lines on microstrip and stripline.

High-frequency signals flowing through PCB traces generate changing electric and magnetic fields which couple and induce similar currents in adjacent tracks and cables. All interconnect carrying changing signals can be considered as antennas and any trace that is a good radiator is also a good receiver, i.e. sub-systems that emit EMI are also more susceptible to external RFI.

Firstly, current always flows in a closed loop and it’s always insightful to observe the careful attention given by many engineers to the signal traces in terms of length, width and characteristic impedance, but then totally ignore the other half of the design, by not considering how the forward paths return to their sources. To minimise RFI, keeping the forward and return paths close together will cancel out their magnetic fields and EMI radiation, i.e. limit the total loop area.

The loop inductance in nH for a current flowing through a conductor and returning through a neighbouring ground plane depends on the self-inductance of each and the mutual coupling between them, and can be approximated to be:

Lloop0 H L/W

where μ0 is the permeability of free space (32 pH/mil), H is the space between the layers in mils, and W and L are the width and length respectively in mils. This assumes that current flows uniformly from one edge to the other, however, in practice, the connection to planes is more like point contacts. This increases current density raising self inductance and hence overall loop inductance, and is often referred to as spreading inductance.

In a dc circuit, the return current takes the path of least resistance, however, at the high frequencies used by the latest spacecraft avionics, it takes the path of least inductance, i.e. the reference plane, either VCC or GND, directly above or below the signal trace. This tendency increases as signals get faster and rise/fall times decrease. Every PCB routing layer needs a dedicated, neighbouring reference plane to minimise loop area and cancel the forward and return magnetic fields to limit EMI. To decrease total inductance, we must reduce the self-inductance of the return path by making it as short and wide as possible, i.e. the use of planes, and increase the mutual inductance between the forward and reverse paths by bringing them closer together.

Returning signal currents generate magnetic fields, which if not properly managed, will mutually induce voltages in other traces, e.g. crosstalk, whose magnitude is proportional to the derivative of the driving signal. For this loop antenna, the following equation approximates the return-current density in A/cm, where H is the height of the trace above the ground plane, D the perpendicular distance from the track and Io the total aggressor current in amps. The amplitude of the crosstalk coupled into adjacent traces reduces with the square of increasing distance, as illustrated below. It is the ratio D/H which is important rather than their absolute dimensions, therefore, current density can be expressed in your desired distance unit. As a guide, Figure 2 also lists the percentage of ground plane current contained within a distance of ± D/H from the centre of the trace calculated using the equation below:

equation for DH

diagram and table for distribution of the return currentFigure 2 This diagram illustrates the distribution of return current.

High-speed signals want to return directly underneath their tracks as this represents the path of the lowest impedance and the closest and smallest loop area. This must be engineered through the design of the PCB stack and layout to limit EMI, and most EMC problems associated with high-speed avionics are due to return currents flowing where they were never intended. Inductance is proportional to loop area and large, unintentional return paths generate a bigger voltage drop (ground bounce), whose amplitude increases with frequency and the magnitude of the current. These should be returned to their source as locally as possible!

When you plan your PCB stack, be aware of which plane(s) will be the return path for your high-frequency signals and ensure there is an unobstructed path back to the driver. Otherwise, the reverse current will find an alternative route back, increasing its loop area and inductance, with its electro-magnetic field coupling with the fringe fields of other traces inducing crosstalk into these victim tracks. The unintentional path has become a loop antenna.

As long as no discontinuities exist in the reference plane, e.g. a split or a via, the return current remains closely-coupled to the forward signal and a transmission line is created. No matter the cause of the slot or discontinuity, the return signal will be unable to travel directly underneath the intended trace. This in turn increases loop area, inductance, and the strength of the forward and return electric and magnetic fields, raising the probability of crosstalk and EMI.

If our high-frequency PCB is enclosed within a box with no openings (Faraday cage), all the internally generated electric and magnetic fields would be contained within this housing and there would be no need to common the signal and power returns to the chassis, i.e. a star ground. However, in reality, avionics products have apertures for I/O and power connectors which attach to cables.

Cables are typically the longest parts of a system and act as efficient antennas that pick-up and/or radiate noise. Coupling can occur capacitively, through the interaction of electric fields, inductively via magnetic fields, or electro-magnetically. The induced voltage can be reduced by increasing the physical separation between the conductors or by shielding, both of which decrease mutual capacitance/inductance.

An unshielded cable has its conductors directly connected to the internal circuit; intended signals as well as unintentional noise can couple onto the I/O lines. A shielded cable can minimise external emissions provided the shield is connected to the chassis using a low-impedance path. Typically, I screw the connector shell directly to the case avoiding the need for a pigtail wire, which adds unnecessary inductance between the returns. Proper shielding continues the Faraday cage and must be connected to the metal connector shell. The EMI from imperfect shielding is caused by radiation through an opening or common-mode currents present on signals within cables.

image compares unshielded and shielded cablesFigure 3 This image shows the difference between unshielded and shielded cables.

A major cause of EMI emissions is unintentional common-mode currents on external cables and shields relative to the chassis. Any impedance between the chassis and the PCB’s ground will generate a voltage between them, appearing as a source on the I/O signal and reference wires. Stand-offs are often used to position the PCB within an enclosure and to common its return to the chassis ground. Care is required to minimise the resistance and inductance of this connection and I prefer non-conductive spacers to reduce overall loop area, and use the outer shell of the I/O and power connectors to provide a more direct and lower-impedance common between the PCB reference and the chassis.

A differential-mode signal (not to be confused with a differential pair) is defined as an intended net that travels along a forward trace and returns on the neighbouring ground plane. Differential-mode radiation results from the currents flowing through intentional loops formed by the conductors of a circuit, which act as small loop antennas radiating magnetic fields. A common-mode signal, however, returns through a different, unintended path. The problem with this is that we do not know where it flows and how it returns, and to minimise EMI, we need to limit loop area.

As energy from stray fields couples to both forward and return currents, common-mode signals are typically illustrated traveling in the same direction. Given that this violates Kirchhoff’s Law that current must flow in a loop, how are common-mode signals even possible? Conducted and radiated EMI are interrelated: a source of RFI in one part of a board can produce the other elsewhere.

Common-mode radiation is the result of undesired voltage drops in the circuit that cause some parts of the system to be at a potential above true ground. When external cables are connected to the system, they are driven by this voltage, forming antennas which radiate electric fields. As illustrated in Figure 2, a portion of the return current spreads outward on the reference plane to find the path of least impedance back to the source. Intentional (differential-mode) high-frequency signals routed near the edge of a PCB generate near-field emissions which become sources that excite openings, cables, and connectors. Similarly, interrupting the return current path either by routing a critical net over a split in a plane, or vertically by changing reference layers, increases loop size and hence inductance, raising the probability of interaction with other signals and inducing crosstalk elsewhere.

NASA’s handbook Electrical Grounding Architectures for Unmanned Spacecraft provides guidelines on creating a common reference between avionics sub-systems and the chassis, as well as discussing different return-current topologies.

Spacechips uses the following PCB design-for-EMC best practices:

  1. Limit the slew rate of high-frequency signals by minimising current amplitudes, edge rates, and switching rates without impacting performance and timing margins.

  2. All high-frequency signals are routed within buried layers next to their ground plane (one dielectric layer away) to provide the lowest impedance return path, limit loop area, and contain electric and magnetic fields. The use of stripline is also particularly effective against inductive crosstalk.

diagram of stripline containment of electric and magnetic fieldsFigure 4 Stripline containment of electric and magnetic fields is shown here.

  1. High-frequency signals do not change reference layers, only sides of the same layer to provide the lowest impedance return path and limit loop area.

  2. The top and bottom layers are ground planes to minimise EMI emissions and, because of their shielding action, reduce susceptibility to external RFI. Transmission-line parameters differ for microstrip and routed tracks are more prone to crosstalk.

  3. Stacks contain separate ground layers for signal and power return (or bus return), which are commoned at the chassis using the outer metallic shell of power and I/O connectors.

  4. High-frequency signals are never routed over splits in power and return planes.

  5. Assigning a power plane next to a ground plane provides a low-inductance, high-capacitance interplane capacitor, decoupling and minimising EMI up to GHz frequencies.

  6. Route high-speed traces on different layers to I/O signals separated by ground layers to minimise crosstalk.

  7. Component, connector, and pin placement are important to minimise track lengths and contain fields. Unit-to-unit connection using 360° attachment of cable shield to the metal chassis.

  8. Extreme care when routing high-frequency signals near the edge of a PCB where there is an opening. The use of the grounded guard traces, the 20-H rule and stitching vias can limit near-field fringe effects around the periphery of boards. Keep case openings small, e.g. 0.25 λ or less, to preserve a Faraday cage, otherwise, slot acts as a waveguide radiating energy into free space.

Spacechips has further grounding and design-for-EMC guidelines for differential pairs, switch-mode regulators, and mixed-signal devices that we teach on our global training courses. In my next post, I will discuss how to segregate noisy digital return currents from sensitive analogue circuitry for ADCs and DACs.

To conclude, grounding and design-for-EMC are system-level issues which need to be considered before beginning circuit design and layout. When developing your PCB stack, have a strategy that explicitly considers the return current paths and their potential to induce crosstalk into other traces, as this will provide the best chance for success in lowering conducted and radiated EMI emissions. Common-mode currents are generated by intended nets that we fail to control and contain. Unintentional signals, which originate from intended ones, are the cause of more than 90% of EMI emissions from a PCB. Be proactive, and design with EMC and right-first-time success in mind!

Until next month, the first person to tell me how ground loops are created will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to Vicky from Canada, the first to answer the riddle from my previous post.

This article was originally published on EDN.

Dr. Rajan Bedi is the CEO and founder of Spacechips, which designs and builds a range of advanced, L to Ku-band, ultra-high-throughput on-board processors and transponders for telecommunication, Earth-observation, navigation, Internet, and M2M/IoT satellites. Spacechips’ Design Consultancy Services develop bespoke satellite and spacecraft sub-systems, as well as advising customers how to use and select the right components, and how to design, test, assemble, and manufacture space electronics. The company teaches grounding and design-for-EMC on its training courses.

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