As the data rates in high-speed digital designs increase, the limits for overall system jitter become tighter. This especially applies to the various components of the clock tree, where the jitter limits for reference clocks, clock buffers and jitter attenuators are even tighter. Due to their high phase noise sensitivity, phase noise analyzers are the […]
Meeting the efficiency challenge of RF front ends (RFFE) is increasingly difficult at higher operating frequencies and bandwidths, such as those proposed for 5G. There is a group of transmitter RFFE architectures whose signal output is constructed from two, or more, efficiently generated components. The architecture of their signal construction uses predictive, post-correction linearization. Their […]
Doherty designs achieve high efficiency, greater linearity and increased output power. Get deep insight into your design with a dual-path, precisely synchronized source driving the Doherty amplifier and improve your yield. The admin of this site has disabled the download button for this page.
Increasing data rates in high-speed digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter attenuation. Modern designs often follow a two-stage architecture, consisting of a jitter-attenuator and a frequency-synthesizer stage. Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice […]
Production test is a necessity that prevents major quality issues in your products that represent the company brand in the hands of customers. The costs, however, can be signiﬁcant and are often greatly misunderstood. For instance, how would you quantify the positive business impact of high-quality products or shortened time to market? Best-in-class organisations are […]