Should you operate your step-down converter in power-save or forced PWM mode?

Article By : Chris Glaser

Power supply designers should select optimum operating mode for each voltage rail based on how it affects system-level performance.

When it comes to step-down converters, also known as buck converters, a designer has to make many design choices that affect the resulting performance of overall system, including the choice of which operating mode to use. While some devices have numerous specialized operating modes, most step-down converters offer just two: power-save mode (PSM) and forced pulse-width modulation (FPWM) mode. The fundamental difference between the two modes occurs at light loads; PSM increases efficiency at light loads while FPWM mode maintains a higher switching frequency and a lower output voltage ripple.

Which operating mode to choose entirely depends on the purpose of the particular step-down converter in the system and the goals of the entire system. This article will explain the differences between PSM and FPWM modes and compare and contrast two step-down converter designs—one for an optical module and one for a wireless headset—to identify the optimum operating mode for obtaining the optimum system-level performance.

FPWM mode operation

FPWM mode is the simplest mode, operating the device at its nominal switching frequency in continuous conduction mode (CCM). Most step-down converters exit PSM and automatically operate in PWM mode at higher load currents.

For an ideal step-down converter in FPWM mode, the output voltage and switch-node (SW) waveforms do not change as the load current changes. This means that two primary contributors to the load’s performance—the output voltage ripple and switching frequency—do not change. Regardless of how much current is consumed, the load is always powered by the same signal and therefore should give the same performance.

The trade-off with this constant ripple and switching frequency is that the step-down converter is always switching, even at light loads. Constant switching means that the switching losses remain the same, even as the load current and thus the output power decreases. This equates to lower efficiency at lighter loads, especially as the load decreases down into discontinuous conduction mode (DCM).

PSM mode operation

Numerous PSM modes are available in the market, each with their own specific behavior. All of them increase efficiency at light loads—above what FPWM mode provides—by reducing the switching frequency in order to reduce switching losses. A constant on-time (COT) topology called DCS-Control uses a simple, single-pulse PSM to provide high light-load efficiency and low output voltage ripple. The load current at which the topology changes from PSM to PWM mode is the DCM to CCM boundary.

PSMs also have a lower quiescent current (IQ) than FPWM modes because many internal circuits are turned off when the device is not switching. This lower IQ, combined with lower switching losses, further boosts efficiency compared to FPWM mode.

The downside of higher light-load efficiency is an increased output voltage ripple and a lower switching frequency, both of which can affect the performance of some loads such as radios. DCS-Control’s PSM is specifically designed to overcome such challenges and successfully powers sensitive loads.

Below are the key highlights of the design areas impacted by the choice between PSM and FPWM modes.

Output voltage ripple

Figure 1 shows the output voltage ripple of the same device under the same operating conditions (3.3 VIN, 1.8 VOUT, no load) for both PSM mode (Figure 1a) and FPWM mode (Figure 1b).

(a)(b)

Figure 1 A view of output voltage ripple at no load for PSM mode (a) and FPWM mode (b). Source: Texas Instruments

DCS-Control’s PSM outputs a single pulse at a time, which creates a vertical increase in the output voltage. This spike is followed by an off-time, without switching, in which the load draws its current only from the output capacitor. This decreases the output voltage until a certain level, when another single pulse occurs. The resulting 18-mVp-p output voltage ripple in PSM is clearly larger than the 5 mV in FPWM mode, but is only 1% of the output voltage. The additional ripple also averages up the measured root-mean-squared (RMS) output voltage, which results in a wider tolerance of the output voltage. Adding additional output capacitance reduces this ripple and improves the output voltage tolerance, if required.

Switching frequency

Figure 2 shows the measured switching frequencies in PSM and FPWM modes with 1.8 VOUT. FPWM mode maintains the higher switching frequency at light loads, whereas the PSM frequency continues to decrease as the load current decreases.

Figure 2 The chart shows switching frequency versus load current for PSM mode and FPWM mode. Source: Texas Instruments

The timescale on Figure 1 also reflects the different switching frequencies of PSM and FPWM mode under the extreme no-load operating condition in which the switching frequency is the lowest. For single-pulse PSMs such as DCS-Control, Equation 1 estimates the switching frequency at a specific load. To calculate the lowest frequency, use the step-down converter’s minimum load current in the equation.

 

 

(1)

Efficiency boost

The main reason to operate in PSM is to increase the efficiency—and thereby reduce the input current—at light loads. Figure 3 shows the dramatic efficiency increase between PSM and FPWM modes. The efficiency difference is most apparent when using a logarithmic scale for the load current on the x-axis. This best shows the light-load region—below a few hundred milliamperes (mA) of load current—where the efficiencies start to diverge.

Figure 3 The chart highlights efficiency versus load current for PSM mode and FPWM mode. Source: Texas Instruments

In FPWM mode, the efficiency begins decreasing when the fixed switching losses become a significant percentage of the decreasing output power. In PSM, the efficiency decreases when the IQ becomes a significant percentage of the load current. In this example, the IQ of 4 µA begins decreasing the efficiency around a few hundred microamperes of load current. Lower-IQ devices maintain the same high efficiency down to lower load currents.

System-level performance

The trade-off of light-load efficiency versus lower output voltage ripple and higher switching frequency has system-level implications. For example, battery-powered systems such as wireless headsets usually use PSM, since the higher efficiency at light loads reduces the input current and thus prolongs the battery runtime. Some rails in battery-powered systems may not operate with a light load, however. The load current may either be high—where the step-down converter operates in PWM—or the load current may be zero, in which case the step-down converter might be shut down completely. These rails may not benefit from the increased light-load efficiency.

On the other hand, non-battery-powered systems such as optical modules typically prefer FPWM mode. In these systems, the efficiency gain is insignificant compared to the lower ripple and higher frequency operation, which can affect the sensitivity and performance of the signal-chain components. Here, again with non-battery-powered systems, there are exceptions that use PSM. Systems that require limited input power consumption, such as those meeting energy-efficiency requirements—for example, Energy Star—and those operating from current-limited input sources—for example, USB ports—may greatly benefit from the reduced power consumption at light loads.

That’s why choosing PSM or FPWM mode has system-level performance implications for rails that operate with light loads. The higher efficiency of PSM generally benefits battery-powered systems, while the lower output voltage ripple and higher switching frequency of FPWM mode benefits systems where the step-down converter’s supply voltage has a strong impact on the load’s performance. As a power-supply designer, you need to select the best operating mode for each rail in your system based on how it affects your system-level goals.

This article was originally published on Planet Analog.

Chris Glaser is senior applications engineer at Texas Instruments.

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