SiC power module packaging solutions for MV grid applications

Article By : Sonu Daryanani

This article summarizes work done by Professor Christina DiMarino and her group at the Virginia Tech CPES on high-density, high-speed 10-kV SiC power module packaging.

Some of the power-electronics applications in medium-voltage (MV) power-distribution and -conversion applications in the range of 1–35 kV include grid-tied inverters and DC/DC converters for renewable energy systems like solar, power management and interruption devices, such as solid-state circuit breakers, DC/DC converters for DC microgrids1 and battery-storage systems needing bidirectional inverters.

These applications have traditionally relied on silicon (Si)-based devices like insulated-gate bipolar transistors (IGBTs). Due to their material advantages, including a wider bandgap, lower intrinsic carrier density, higher thermal conductivity and higher saturation velocity, silicon carbide (SiC) power devices offer a number of advantages over Si. These include a lower specific on-resistance (RDS(on)) for a given voltage rating, a higher voltage rating than that available with Si (e.g., up to 15 kV for SiC MOSFETs, versus 6.5 kV for Si IGBTs) and much lower capacitances due to smaller die sizes for a given RDS(on). Combining the benefits of lower conduction and switching losses, higher switching frequencies and simpler cooling requirements can translate to lower power-conversion loss, improved efficiency, simpler converter topologies and significantly improved high-temperature ratings and performance, as well as reduced size, weight and system costs.

Packaging of these high-voltage (HV, >3.3-kV–rated) SiC devices and modules for use in these MV grid applications poses several challenges. This article summarizes work done by Professor Christina DiMarino and her group at the Virginia Tech Center for Power Electronics Systems (CPES) on high-density, high-speed 10-kV SiC power module packaging. CPES focuses on research and development dedicated to improving electrical power-processing and -distribution systems, including power-conversion architectures, power-electronics components, modeling, power quality and high-density integration.

Challenges in HV SiC device/module packaging

  • Due to their faster switching speeds, SiC devices are more sensitive to parasitic inductances from the packaging. These can resonate with the device capacitances, causing undesirable electromagnetic interference. During high-speed current transients (di/dt), large overvoltages can be created across the device, which can degrade device reliability or cause catastrophic fails.
  • Parallel devices are often used to achieve module current ratings. Imbalances in parasitic inductances/capacitances or static device parameters like the threshold voltage can result in varying transient voltage overshoots across the paralleled die. Die with higher overshoots will see greater switching losses and thus higher temperatures. This can reduce module lifetimes. External gate resistors are commonly added to control overshoots; however, these increase switching times and hence losses. Low-inductance wire-bondless interconnect schemes have been proposed, for example, with metal-post–interconnected parallel plates.2 Decoupling capacitors can be used to mitigate the impact of parasitic inductance. One approach places the capacitors above the power device, creating a vertical power loop that keeps the horizontal module footprint unchanged.3
  • Traditional power modules include a parasitic capacitance across the insulating ceramic substrate (such as direct-bonded copper, or DBC) to the heatsink, which is generally at ground potential. Under higher-voltage transients (dV/dt), this capacitance becomes a path for common-mode (CM) current to flow through the system ground. Filters and chokes can mitigate this; however, they add cost and complexity. A screen layer can be added with the use of multilayer ceramic substrates, which returns the CM current back to the die while also reducing high-frequency noise.4
  • The high electric field created in these HV devices can exceed the breakdown strength of dielectric materials in the packaging. This can create partial discharge (PD), which can damage the insulating ceramic substrate. Reducing the electric field, and thereby increasing the PD inception voltage (PDIV), near the insulating substrate is key, as this is typically where the PD occurs.5

Figure 1 shows some of these challenges discussed above.

Challenges with power module packaging.
Figure 1: Challenges with power module packaging

High-density, high-speed 10-kV power module packaging proposal

DiMarino’s group at CPES has proposed an innovative package solution for a 10-kV, 350-mΩ SiC power module with high switching speed, improved HV performance and lower CM current.6 Experimental validation has also been done on the key aspects of this proposed package. Figure 2 shows the schematic and 3D model of the half-bridge module.

Proposed 10-kV package.
Figure 2: Proposed package — (a) schematic; (b) bottom stacked substrates with six 10-kV MOSFET die and posts; (c) top stacked substrates with embedded decoupling capacitors; (d) side view showing vias and PCB; (e) module with spring terminals; (f) housing with integrated direct-substrate cooler

Some of its main design and assembly characteristics are discussed below:

  • The half-bridge module has three 10-kV SiC MOSFETs per leg. No external anti-parallel diodes will be used. Significant improvements in the SiC MOSFET body diode enable symmetric reverse conduction with low recovery losses.7
  • The module footprint is 74 × 49 × 11 mm without the housing, which gives a power density of 13 W/mm3. The added housing and integrated cooler result in a net power density of 4 W/mm3.
  • In power modules, the electric field concentrates at the intersection of the ceramic, metal and encapsulation,5 known as the triple point. Stacking DBC substrates can reduce electric field within the bulk ceramic and at the critical triple points.8 The worst-case field is produced when the low-side switch is conducting. Simulations of the electric field under this condition concluded that in the stacked ceramic approach, the middle metal layer should be connected to half the DC bus voltage, i.e., 5 kV in this case. The peak electric field is reduced by 58% compared with the single substrate case, and it’s uniformly distributed within the two bulk ceramic substrates. The implementation of creating the half bus is done with a pair of 5-kV ceramic decoupling capacitors, as shown in Figure 2(c). The midpoint 5-kV connections of the capacitors are done with metal posts and vias, as shown in Figure 2(d), and connected to the middle metal layer of the bottom DBA stack. The proposed module has a planar sandwich structure. Four substrates were used, as shown in Figure 2(d), with two (DBA1, DBA2) beneath the die and two (DBA3, DBA4) above. The stacked substrate approach effectively increases the PDIV. A pressure-assisted silver (Ag) sintering process was developed for bonding the 50 × 50-mm bottom and the 35 × 75-mm top stacked substrates. Ag sintering has advantages of low void content, higher thermal conductivity and reliability than solder and the ability to undergo multiple sintering cycles without affecting previously sintered joints. After the printed paste is applied and dried, 1 MPa of pressure was applied in a hydraulic press, with the temperature increased to 260˚C for sintering. The substrates are cooled under uniform pressure to prevent the CTE mismatch between the aluminum (Al) and aluminum nitride (AlN) from bending or cracking. Line thermal resistance of 0.11–0.14 K/W was measured, which indicates good uniformity.
  • Metal posts made of molybdenum (Mo) are used to increase the distance and thereby reduce the electric field between the die and the top substrate. Mo is chosen for its low CTE. Pressure-less and pressure-assisted Ag sintering methods were tried for the post attachment, yielding similar results for bonding strength. The optimal post height is a tradeoff between electromagnetic and electrostatic performance, with a shorter post reducing parasitic inductance and resistance but increasing electric field strength. The field needs to be below the breakdown strength of the encapsulation material. Simulations of the electric field distribution show significant reduction in the field when the post height was increased from 1 to 2 mm; hence, a 2-mm height was chosen.
  • The S1D2 node shown in Figure 2(a) experiences high dV/dt as it switches between D1 and S2. To divert the resultant current seen at the system ground back to the DC bus,9 the intermediate metal layer in a stacked DBC arrangement can be tied to either the positive or negative bus. The amount of current diverted back will depend on the high-frequency impedance of the connection back to the DC bus; hence, the implementation of this CM screen is critical. Connecting the middle metal layer to the midpoint of the decoupling capacitors creates a low-inductance path for the CM current flow, balances and reduces the power-loop inductances for the MOSFET switch pairs and reduces the peak electric field at the triple point.
  • The resulting module has a power-loop inductance of 4.4 nH/MOSFET pair,10 which is one of the lowest reported for 10-kV SiC power modules to date.
  • The housing has a significant impact on the overall size, thermal resistance and voltage rating. Figure 3 shows the housing design. The external bus bar is mounted on top and pressure applied through mounting screws. The pressure compresses the springs until the bus bar contacts the protrusions in the housing lid. Because the springs are not exposed, creepage and clearance restrictions do not apply. The protrusions create defined air gaps between the housing lid and the bus bar, which can be adjusted to trade off the PDIV and parasitic inductance/resistance from the added connection distance. A larger gap will increase PDIV as well as the parasitics. A 1-mm protrusion height was chosen. Even with this, as shown in the electric field simulation in Figure 4(a), the field strength exceeds the 3-kV/mm breakdown in air. Hence, field-control plates within the bus bar are proposed, which are at the same potential as the spring terminals, and serve to shift the peak electric field from air to the solid insulation within the bus bar, as shown in Figure 4(b).
Housing showing bus-bar arrangement.
Figure 3: Housing design — (a) module with housing and lid; (b) module with the bus bar; (c) side view of the module; (d) module with the bus bar compressing the spring terminals
Simulated electric field distribution with and without field-grading plates in the PCB.
Figure 4: Simulated electric field distribution — (a) without and (b) with field-grading plates within the bus-bar PCB
  • Baseplate and thermal grease for cooling can increase net thermal resistance and create bending stress on the ceramic substrates. In the proposed package, the bottom DBA is scaled to the housing and a targeted jet-impinged cooling system is used, which injects coolant directly onto the lower surface of the substrate.11
  • Ag sintering was chosen for the die attach due to its lower thermal impedance and thermal cycling capability compared with solder. Because the 10-kV SiC MOSFET die have gold (Au) backside metallization, and Ag diffuses faster than Au, a sintering profile is needed to limit Ag diffusion and prevent void formation. Hence, 230˚C at 90 minutes was used in this study. Average shear strength of 15 MPa was achieved. Applying pressure can improve this to about 25 MPa but adds complexity when sintering multiple die simultaneously.
  • A prototype module was built in which the springs used had a continuous current rating of 10 A. The housing and integrated jet-impingement cooler was 3D-printed out of high-temperature resin. A Si gel with low viscosity was chosen for the encapsulation due to its simple processing and good reliability with fewer air pockets.

Table 1 lists the process steps and materials selected for the module prototype.

Summary of packaging processes and materials used for the 10-kV module.
Table 1: Packaging processes and materials selected for the 10-kV SiC module

Prototype test results

Figure 5 shows the switching performance of the module using a double-pulse test with two SiC 10-kV MOSFETs. The tests were done at 5 kV and 20 A with turn-on and turn-off gate resistors of 0.33 and 0.17 Ω. Table 2 lists the transient parameters from this test. Negligible overshoot and ringing were observed, indicating low gate-loop and source-loop inductances. These results are some of the fastest switching speeds reported for similarly rated SiC MOSFETs and IGBTs.

The effectiveness of the CM screen was measured using an RF current transformer in the ground path with a bandwidth of 200 MHz. Figure 6 shows the turn-off waveforms with three MOSFETs in parallel. The dV/dt is 25 V/ns at a 2-kV bus voltage. As shown, the CM screen lowers the ground-current overshoots from 2 A to 0.2 A, validating its effectiveness.

Switching waveforms with DPT test on module prototype.
Figure 5: Switching waveforms for the 10-kV module prototype
Summary of prototype switching results.
Table 2: 10-kV, 350-mΩ SiC MOSFET module prototype switching results
Measured drain-source and ground currents showing effect of CM screen.
Figure 6: Switch-off waveform showing ground current with and without the CM screen

PD tests were conducted using a 50-kV, 60-Hz AC excitation source and a PD sensor. These tests were completed on both the internal stacked substrates as well as the PCB bus bar with internal field grading. A patterned, 1-mm–thick AlN-DBA substrate with 2-mm spacing between metal traces was used to compare the single substrate with the stacked substrates, in which the middle metal is at half the applied voltage.

As shown in Table 3, the PDIV on the stack when the middle metal is connected to half the applied voltage shows an increase of 53% in air and >40% with encapsulation when compared with the single substrate case. The PCB bus bar with internal field-grading plates was also verified using PD tests. As shown in Table 3, the bus bar demonstrated a PDIV of 12.4 kV in air and 11.6 kV in air with a PD dummy module mounted to the bus bar.

PD testing summary.
Table 3: PD testing summary

Thermal characterization of the prototype module showed a lowest junction-to-ambient specific thermal resistance of 26 mm2·K/W (0.38 K/W).11

In conclusion, DiMarino said, “At CPES, we have proposed a high-density, high-speed module package for 10-kV SiC MOSFETs that could be used in a variety of MV power-conversion and -distribution applications. Our package approach focuses on low parasitics, reducing CM current, achieving high PD voltages and lowering thermal resistance. With this, we can truly take advantage of the superior SiC material characteristics and create highly efficient solutions in this voltage space.”

References

1Wang, F., and Ji, S. (March 2021). “Benefits of high-voltage SiC-based power electronics in medium-voltage power-distribution grids.” Chinese Journal of Electrical Engineering, Vol. 7, No. 1.

2Haque et al. (1999). “An innovative technique for packaging power electronics building blocks using metal posts interconnected parallel plate structures.” IEEE Transactions on Advanced Packaging, Vol. 22, No. 2, pp. 136–144.

3Hoene, E., Ostmann, A., and Marczok, C. (February 2014). “Packaging Very Fast Switching Semiconductors.” 8th International Conference on Integrated Power Electronics Systems.

4Huber, T., Kleimaier, A., and Kennel, R. (September 2017). “Ultra-low inductive power module design with integrated common mode noise shielding.” 19th European Conference on Power Electronics and Applications.

5Bayer et al. (March 2016). “Enhancing partial discharge inception voltage of DBCs by geometrical variations based on simulations of the electric field strength.” 9th International Conference on Integrated Power Electronics Systems.

6DiMarino et al. (March 2020). “Design and Experimental Validation of a Wire-Bond-Less 10-kV SiC MOSFET Power Module.” IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 8, No. 1, pp. 381–394.

7Passmore et al. (2016). “The next generation of high voltage (10 kV) silicon carbide power modules.” IEEE Workshop on Wide Bandgap Power Devices and Applications.

8Hohlfeld et al. (March 2012). “Stacked substrates for high voltage applications.” 7th International Conference on Integrated Power Electronics Systems.

9Domes, D. (May 14, 2013). Semiconductor arrangement. U.S. Patent 8441128B2.

10DiMarino et al. (October 2017). “Design of a novel, high-density, high-speed 10 kV SiC MOSFET module.” 2017 IEEE Energy Conversion Congress and Exposition.

11Mouawad et al. (May 2018). “Development of a highly integrated 10 kV SiC MOSFET power module with a direct jet impingement cooling system.” IEEE 30th International Symposium on Power Semiconductor Devices and ICs.

 

This article was originally published on Power Electronics News.

 

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