Space-grade FPGAs can be re-programmed in-orbit

Article By : Rajan Bedi

Re-programming SRAM and flash-based space-grade FPGAs in-orbit offers flexibility to change functionality and improve system performance in response to changing needs.

SRAM and flash-based space-grade FPGAs can be re-programmed in-orbit offering maximum flexibility to change functionality and improve system performance in response to changing needs. For technology demonstrator satellites, multiple experiments can be realised using a single payload, minimising on-board processing hardware. Deep-space missions can be launched early to exploit shorter planetary orbits with the knowledge that the FPGA firmware can be up-linked and deployed when needed.

Ordinarily, Xilinx’s space-grade and radiation-tolerant FPGAs are configured in Master SPI and BPI modes. For in-orbit re-configurability, an external device such as an embedded microprocessor can control the SelectMap interface with the FPGA operating either in Slave Serial or Slave SelectMap modes. Either a MPU or the FPGA can select between multiple configuration bitstreams pre-stored in external flash memory, or these can be up-linked to the spacecraft and then transferred to the avionics on-board storage using industry-standard interfaces, such as SpaceWire or CAN.

Taking Xilinx’s XQRKU060 FPGA as an example, in Slave SelectMap mode, after INIT_B goes high, parallel data can be loaded into the FPGA’s configuration memory (via multiple function pins in bank 65) on each rising edge of CCLK, with an MPU (or a non-volatile FPGA) generating the latter.

Xilinx diagram of Slave SelectMap configuration mode
Figure 1 This is an example of the Slave SelectMap configuration mode for the XQRKU060 FPGA. Source: Xilinx

In Slave Serial mode, after INIT_B goes high, one bit of data is loaded into the FPGA’s configuration memory (via the D01_DIN pin in bank 0) on each rising edge of CCLK, with the MPU generating the latter. After configuration is complete, the SPI interface to the external flash memory typically remains unused, however, Xilinx’s STARTUPE3 primitive allows read and write access to this port enabling a new bitstream to be uploaded. Multiple images or application data can also be written provided there is spare capacity.

Xilinx diagram of slave serial configuration modeFigure 2 This block diagram shows the Slave Serial configuration mode. Source: Xilinx

Xilinx’s XQRKU060 FPGA also offers a MultiBoot feature to allow you to store multiple bitstreams in external flash memory and then select between these in-orbit. Master SPI and BPI modes are supported and MultiBoot is initiated by using the internal PROGRAM (IPROG) command to reconfigure the FPGA. This is similar to pulsing the PROGRAM_B pin, however, IPROG does not reset the dedicated configuration logic nor does it erase the WBSTAR, TIMER, BSPI, and BOOTSTS registers used to initiate MultiBoot. The IPROG command can be issued through the ICAP, which is controlled by user logic, or can be embedded within the bitstream, allowing systems to re-program themselves in-orbit. The IPROG command instructs the FPGA to load a new image from the address specified in the WBSTAR register, and if there is an issue such as an IDCODE, CRC, or time-out error, a fallback facility exists to restore the original golden bitstream as illustrated in Figure 3.

Xilinx MultiBoot flow diagramFigure 3 This flow diagram shows how to use the MultiBoot feature to select multiple bitstreams. Source: Xilinx

Partial re-configuration can also be used to dynamically re-program specific regions in-orbit: active partitions within the fabric can be updated without comprising the integrity of applications running elsewhere within the FPGA that use the imported logic. Re-configurable modules can be swapped in and out as needed using the ICAP or SelectMAP as illustrated below:

diagram of partial re-configuration of specific user logic blocks Figure 4 Partial re-configuration of specific user logic blocks can dynamically re-program specific regions in-orbit. Source: Xilinx

The main configuration (shown in blue above) uses a static, top-level place and route implementation and imported partitions have to respect this. This allows the FPGA to time-multiplex between different tasks and partial bit files can be as small as one frame or as large as the complete bitstream. Unlike the other in-orbit re-programming methods, partial re-configuration does not totally disrupt the operation of the complete FPGA.

For the XQRKU060, enabling the PERSIST bitstream option maintains the configuration logic access to the SelectMAP port after configuration for readback access. The PERSIST option can be used to re-configure the FPGA using an external device such as a microcontroller, without pulsing the PROGRAM_B pin or using the JTAG interface.

For the Microchip ProASIC3, RTG4, and RTPolarFire flash-based FPGAs, an external microprocessor can control their JTAG interfaces to re-configure devices in-orbit. Microchip’s DirectC software manages the handshaking between the MPU and the target FPGA, as well as the transfer of the configuration data. DirectC can be freely downloaded and requires 256 bytes of storage on the host MPU.

Microchip flow diagram of the DirectC softwareFigure 5 DirectC software manages in-orbit re-configurability. Source: Microchip

Ordinarily, NanoXplore’s space-grade FPGAs are configured using Master SPI mode, however, a number of parallel slave modes as well as a JTAG interface also exist to allow an external device such as a microprocessor to control the I/O and generate a configuration clock. Furthermore, a dedicated SpaceWire port exists within the program bank to directly update in-orbit the FPGA’s bitstream using this avionics standard as illustrated in Figure 6. The external flash is not updated!

diagram of the Nanoxplore SpaceWire portFigure 6 A dedicated SpaceWire port can directly update in-orbit the FPGA’s bitstream. Source: NanoXplore

To continue the discussion on Scrubbing and In-Orbit Re-Configuration of Space-Grade FPGAs, I will be presenting a talk at the MEWS Conference to be hosted by JAXA in Japan on the 28th and 29th of October. This will be an online presentation and you can register now. I will also be presenting an online poster on this topic at NASA’s SEE/MAPLD Workshop, to be held October 6-8.

Which space-grade or COTS FPGA should you use on your next mission? To assist your device selection, Spacechips has a dedicated lab to test and compare your in-orbit reconfigurable processing requirements and allow you to make informed technology selections.

photo of the Spacechips FPGA laboratoryFigure 7 Spacechips’ FPGA laboratory provides device testing and comparison.

Spacechips offers scrubbing and in-orbit re-configuration solutions and teaches these in its FPGA training course. Until next month, the first person to tell me the in-orbit re-programming options for Xilinx’s V4 and V5QV FPGAs will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to Peter from Portland, USA, the first to answer the riddle from my previous post.

This article was originally published on EDN.

Dr. Rajan Bedi is the CEO and founder of Spacechips, which provides ultra high-throughput on-board processing and transponder products, design consultancy in space electronics, training, technical-marketing, and business-intelligence services. Rajan can also be contacted on Twitter.

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