Here is a precision integrator that generates a pulse train whose frequency is proportional to the ratio of two input currents.
The design idea in figure 1 employs the S1 switch of the Texas Instruments IVC102 precision integrator to select between a single input current or the superposition of two input currents. This function allows you to obtain an output signal whose characteristics directly relate to the ratio between the two input currents. The circuit achieves high accuracy independent of most of the system parameters. In addition, you can enhance accuracy if you let a digital counter control the IVC102-based circuit (figure 2). In this case, the system's output is a number in the BCD (binary-coded-decimal) format proportional to the input-current ratio, realising a true digital conversion.
Figure 1: This circuit allows you to obtain an output-signal frequency that directly relates to the ratio between the two input currents.
The circuit divides into two phases. The first phase begins when the output voltage of the IVC102 becomes slightly greater than the threshold voltage of the LM311 comparator. The comparator generates a falling-edge signal, and the 555 monostable starts a pulse, which closes S1. In this case, the total input current, I2–I1, generates a negative-going ramp if I2 is greater than I1. In the delta-time period, ΔTA, the integrator's output voltage reaches the final voltage value. Hence, |VFIN–VTH|=(I2–I1)ΔTA/CINT, where CINT is the value of the IVC102's integrating capacitor. When the 555 monostable's output pulse ends, the second phase starts: S1 opens, and input current I1 discharges CINT. The ΔTB for the output voltage to assume the threshold voltage's value is then CINT|VFIN–VTH|/ I1, and the comparator generates a new trigger command to the monostable so that a new cycle can start. Manipulating the previous equations yields: I1/I2=ΔTAf, where f=(ΔTA+ΔTB)–1. This equation states that the generated output signal, a train of pulses, has a frequency, f, proportional to the I1/I2 current ratio. The accuracy of the monostable directly affects the accuracy of the system. Conversely, the integrating capacitor's and threshold voltage's values do not influence the accuracy if they maintain constant values at least in the 1/f time scale.
Figure 2: To the circuit in Figure 1, this design adds a BCD counter to obtain direct readouts on seven-segment LED displays.
You can increase the accuracy of the circuit in figure 1 by modifying the section that generates the constant, ΔTA-wide pulse. The circuit in figure 2 generates a ΔTA-wide pulse using three HCF40110 BCD counters. When the third counter generates a carry, 1000/fCK seconds have elapsed. In figure 2, a set/reset flip-flop controls S1's state, and the 74HC14 hex inverter with a Schmitt-trigger input generates the pulses that reinitialise the system. A brief description of the measurement cycle follows. When the IVC102's output voltage becomes greater than the threshold voltage, the INH (inhibit) signal connected to the toggle input of the first HCF40110 inhibits counting. At the same time, the negative-going edge of the comparator output generates a negative-going pulse of approximately 10µsec, which latches the counters' values at the output to display the actual result. After this step, a negative-going pulse sets the SR flip-flop to close S1. A corresponding positive-going pulse resets the counters. The latch-enable lines of the 40110s are tied high, so the counters' reset doesn't affect the displayed value. When the reset pulse ends and the comparator's output goes high, the HCF40110s can count up. When the third counter generates a carry (negative-going pulse), the 1000th clock period has elapsed, and the SR flip-flop resets to open S1. The cycle ends at the next falling edge of the comparator's output. The time period in which I2–I1 charges CINT is NA/fCK(NA=1000), and the I1 requires for discharging is NB/fCK. Manipulating the integrator-related relationships yields I2/I1=N/NA, where N=NA+NB.
This article is a Design Idea selected for re-publication by the editors. It was first published on May 24, 2007 in EDN.com.