This article discusses the impact of stitching capacitors in mitigating crosstalk due to imperfect reference plane during signal crossing over split planes on PCB. The investigation was performed with 3DEM simulation to analyze crosstalk in frequency and time domain, and also surface current density of the return path.
In electronic systems, signal transmission exists in a close loop form. The 'forward current' propagates from transmitter to receiver through the signal trace. On the contrary, the 'return current' travels backward from receiver to transmitter through the power or ground plane right underneath the signal trace that serves as the reference or return path. The path of 'forward current' and 'return current' forms a loop inductance. It is important to route the high-speed signal on continuous reference plane so that the 'return current' can propagate on a desired path, directly beneath the signal trace.
When the return path is broken due to the switching of reference planes with different potential, e.g., from ground to power or vice versa after signal crossing over split planes on PCB, the return current might detour and propagate on a longer path, which causes the rise of loop inductance. This might lead to the sharing of common return path by different signals that poses high risk of interference among the signals due to higher mutual inductance. This interference results in signal crosstalk. To mitigate the crosstalk due to imperfect return path, stitching capacitors are mounted on PCB to serve as a bridge between the two reference planes of interest.
Analysis of signal crosstalk with 3DEM modeling
To investigate the impact of stitching capacitor in mitigating signal crosstalk due to imperfect return path during signal crossing over split planes on PCB, three simulation models of 3DEM are constructed using Keysight EMPro. In model 1A (i.e., 3DEM structure illustrated in Fig. 1), two signal traces with 50 ohm characteristic impedance in single-ended mode on top PCB layer are crossing over the split planes. The signal traces are 200 mil long and 5 mil wide. Meanwhile, the gap between the ground and power plane on layer 2 is 20 mil, while the solid ground plane is on layer 3. All the three copper layers have 1.2 mil thickness. FR4 material is used as the PCB substrate.
The two signal traces are separated 15 mil apart (i.e., tripple of the signal trace width for minimum crosstalk due to “forward current” propagation). From crosstalk perspective, port 1 and port 2 terminations serve as the transmitting and receiving end respectively of the aggressor line. On the other hand, port 3 and port 4 terminations serve as the transmitting and receiving end respectively of the victim line.
In model 1B depicted in Fig. 2, a stitching capacitor is placed across the split planes on the right side (i.e., highlighted in red) to connect electrically the two reference planes on layer 2. The rest of the portion is the same as model 1A. This ideal 0.1uF capacitor, without parasitic resistance (ESR) and parasitic inductance (ESL) serves as a single return path in transmission line.
On the other hand, in model 1C depicted in Fig. 3, one more ideal 0.1uF stitching capacitor is placed across the split planes on the left side (i.e., highlighted in red) to connect electrically the two reference planes on layer 2. These two capacitors provide two return paths in transmission line.
S41 parameter or far end crosstalk (FEXT) of the abovementioned 3DEM models are plotted in Fig. 4 (i.e., span from 1 MHz to 3 GHz). A more severe crosstalk is indicated by smaller absolute value in dB. With reference to Fig. 4, the most severe signal crosstalk is experienced model 1A (i.e., -32 dB at 500 MHz), followed by 1B (i.e., -36 dB at 500 MHz) and the least severe by 1C (i.e., -41.5 dB at 500 MHz). Model 1A does not have return path at all. Alleviation of crosstalk as much as 10 dB is achieved by providing more return paths using capacitors to bridge the reference planes on layer 2.
Subsequently, transient simulation is performed for the abovementioned 3 models to observe the phenomenon of FEXT in time domain. In this transient simulation, a square wave signal with 1Gbps data rate (i.e., 500MHz Nyquist frequency), 1.2Vpp amplitude and 5V/ns slew rate is injected into port 1 of each model’s 3DEM model, with port 3 being pulled low (i.e., serves as near end point of victim line), followed by probing at port 4 (i.e., serves as far end point of victim line). Referring to Fig. 5, noise induced at far end point of victim line in time domain for model 1A, 1B and 1C is 135mVpp, 98mVpp and 72mVpp respectively.
The smallest amplitude of noise is induced at far end point of victim line in model 1C due to the least crosstalk incurred, contributed by more return paths provided by the additional stitching capacitor, versus the single return path (i.e., only one stitching capacitor) in model 1B and none return path (i.e., without stitching capacitor at all) in model 1A.
Subsequently, the surface return current density on return path through the stitching capacitor for mode 1B versus 1C is observed, depicted in Fig. 6. When square wave is at 500 MHz Nyquist frequency is injected at both Port 1 and 3 in the same phase respectively, the forward current flows along the two signal traces on the top PCB layer, whereas the return current flows from the power to ground plane on layer 2. The surface return current density for model 1B and 1C, through each stitching capacitor is 60A/m and 32A/m respectively. Current density for model 1B almost doubles versus model 1C because its single stitching capacitor becomes the return path bottleneck to be shared commonly by two signal traces, that increases the mutual inductance and hence crosstalk.
The study is further carried out to analyze the effect of ESR and ESL on mitigating the crosstalk due to imperfect return path. Practically, a discrete capacitor has intrinsic parasitic ESR and ESL in series with it, depicted in Fig. 7. The 3DEM simulation is repeated on the abovementioned model 1C, but varying the value of ESR and ESL in the two stitching capacitors respectively. With reference to FEXT plots in Fig. 8, ESR of 0.15ohm worsens the FEXT by 0.03dB at frequency near 500MHz. Similarly, with reference to FEXT plots in Fig. 9, ESL of 0.5nH intensifies the FEXT by 1.1dB at frequency near 500MHz. Further increase of ESL to 1nH contributes an additional 0.35dB to FEXT.
In fact, the impedance of the stitching capacitor is directly proportional to ESR and ESL. A larger impedance in stitching capacitor due to larger ESR and ESL contributes to higher resistance in the signal return path, that in turn intensifies the FEXT.
It is crucial to provide a continuous return path for high speed signaling during signal crossing over split planes on PCB to minimize crosstalk. Crosstalk due to return path discontinuity caused by switching of reference planes with different potential is reduced by as much as 10 dB, after bridging by the stitching capacitors. Moreover, stitching capacitor with smaller ESR and ESL shall be chosen to provide a low impedance signal return path to achieve minimal crosstalk.
 Kenneth Wyatt, Stitching Capacitors
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