Study of channel loss compensation scheme for DDR5 SDRAM

Article By : Chang Fei Yee, Keysight Technologies

This article provides brief overview of the DDR5 SDRAM and its channel loss compensation scheme, Decision Feedback Equalization.

This article provides brief overview of DDR5 SDRAM and its channel loss compensation scheme, Decision Feedback Equalization. Subsequently, the effectiveness of this scheme in channel loss compensation is studied by analyzing the eye diagram of DDR5 data transmission at 6.4Gbps.


Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) standard was officially released in July 2020. This interface requires 1.1V voltage supply and operates at maximum data speed grade 6.4Gbps. It also has up to 4 taps Decision Feedback Equalization (DFE) to compensate channel loss at the receiver (Rx) input buffer of the data (DQ) line.


The Decision Feedback Equalizer (DFE) is a form of non-linear equalization which relies on decisions about the levels of previous symbols (high/low) to correct the current symbol. This allows the DFE to account for distortion in the current symbol that is caused by the previous symbols. Its main advantage over linear equalizers is the ability to cancel inter-symbol interference (ISI) without amplifying the noise. The DFE’s taps are applied to normalized 1/−1 voltages based on a symbol slicer decision. The tap values are meant to correct for the portion of their symbol that lingers and distorts the current symbol. By setting the optimum DFE tap value, the eye diagram is enlarged to achieve robust DDR5 signal transmission.

Analysis and Results

The effectiveness of DFE in channel loss compensation for DDR5 SDRAM interface at 6.4Gbps is studied by performing pre-layout signal integrity analysis using Keysight ADS, with simulation topology depicted in Figure 1. The transmitter (Tx) buffer has 34Ω series output impedance. Meanwhile, the Rx buffer has 40Ω on-die-termination (ODT) pull up resistor.

The full path channel comprises two PCBs hooked up with a through-hole connector. The 50Ω trace on each PCB is 4-inch long, whereas the multi-board connector has a 60-mil pin tail stub length. The full path channel loss plot is depicted in Figure 2, with -2.5dB loss at 3.2GHz (i.e., fundamental frequency of 6.4Gbps) and -8.5dB loss at 9.6GHz (i.e., 3rd harmonic of 6.4Gbps).

Figure 1: Simulation topology for eye diagram analysis.

Figure 2: Insertion loss plot for full path channel between Tx and Rx.

The eye diagram plots probed at Rx die level with various settings of DFE are shown in Fig. 3. When DFE is turned off, the eye height is 0.393V. Meanwhile, the eye height with 1-tap DFE is enlarged to become 0.42V. On the other hand, the 4-tap DFE yields the largest eye height, i.e., 0.439V.

Figure 3: Eye diagram at Rx with various settings of DFE.


This study indicates that DFE is effective in channel loss compensation for DDR5 SDRAM interface. Iterative trials of DFE tap setting shall be performed to find out the most optimum value, to yield the largest eye diagram for robust DDR5 signal transmission.



  1. JEDEC DDR5 spec

  2. Decision Feedback Equalization,

  3. Keysight ADS,


About the Author

Chang Fei Yee is a Technical Lead in Hardware and SI/PI at Keysight Technologies.


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