Power supply design advances like FFRZVS circuits enable smaller USB PD power adapters for portable devices.
USB has the potential to address the demand for simplifying the design of miniature power adapters by combining interface signals and power in a single cable. Now, in its fourth generation since its introduction in 1996, the Universal Serial Bus (USB) has standardized computer connectivity, replacing interfaces such as serial ports and parallel ports, and has become the cable of choice for charging a wide range of portable devices.
The gigabit speeds specified in USB 3.0 make this bus a strong contender to replace all types of cables associated with PCs and laptops, including displays, external disk drives, printers, and scanners. Most importantly, with the USB power delivery (USB PD) specification, USB also has the potential to eliminate the power cable.
Developed in 2012 to create an interoperable charging standard for all USB devices, USB PD is now on its third revision. It has evolved to charging applications capable of powering hard drives, printers, and similar devices with power levels up to 100 W and voltages between 5 and 20V. The USB cables may soon be the only thing needed to power our laptops, as well as to connect a wide range of peripherals to them. By breaking the previous 7.5 W power limit at 5V, USB PD also creates the possibility of even faster charging of smartphone batteries.
Power supply miniaturization
The design of miniaturized power supplies requires engineers to find a balance between style and efficiency, while ensuring compliance with a multitude of electrical standards and safety requirements. Switch mode power supplies (SMPS) have become common solutions for devices like laptops as their high efficiency significantly reduces power consumption and consequent heat dissipation, enabling them to be packaged into smaller enclosures.
As SMPS design has matured, the quasi-resonant switching converter (QRC) operating in discontinuous conduction mode (DCM) has become the topology of choice for high-density AC-DC designs, as it eases development challenges and offers a more stable loop control than alternatives. A quasi-resonant switching converter, also known as variable frequency or valley switching flyback, makes use of parasitic resonance characteristics to control the turn-on voltage of the switching MOSFET, thereby reducing switching losses (Figure 1).
Figure 1 The basic operation of a quasi-resonant switching converter shows how it uses parasitic resonance characteristics to control the turn-on voltage of the switching MOSFET. Source: Infineon
Figure 1B shows the resonant oscillations in the Vds waveform, caused by the parasitic inductance, capacitance (Lleak) and CD. The resonance results in “valley” points in Vds and, in quasi-resonant (QR) or valley switching flyback, the circuit controller is configured to turn on the MOSFET at the minimum valley point. The controller can be programmed to turn on at different valley points. Where it always turns on at the first valley, it is known as a free running QR flyback. In this mode, the resonant and hence switching frequency varies with the load, with minimum frequency at higher loads.
Despite their advantages, QRC design requires further optimization in order to achieve the densities required by USB levels of miniaturization. Although in low-line situations, the MOSFET virtually operates in zero-voltage switching (ZVS) mode, it’s not the case in high-line situations, leading to significant levels of switching loss. The basic QRC design can be modified to help reduce these losses; a slow reverse recovery diode can push some of the dissipated energy back into the bulk capacitor or output (Figure 1A). It is important to note that while this approach reduces losses at high-line input, it leads to higher losses at low line.
Design considerations such as the use of MOSFETs with higher output capacitance (COSS) as well as low Rds(ON) devices can also help limit conduction and leakage losses. However, the relationship between load and switching frequency poses a further difficulty with QRC topologies with suboptimal transformer utilization at peak power levels. This phenomenon is responsible for common-mode noise interference issues in touchscreen applications.
As pressure on power adapter size increases, manufacturers have begun to simplify production by incorporating windings into the PCB. It requires switching frequencies higher than 100 kHz to minimize copper losses. In these circumstances, forced-frequency resonant zero-voltage switching (FFRZVS) designs offer an optimal solution.
In these designs, switching is implemented at the zero-voltage point in the primary transformer. It reduces the turn-on losses of the power switch and heat dissipation and increases efficiency. The high-frequency operation of FFRZVS circuits enables the size of the magnetic components to be reduced, enabling high-density and compact power supplies.
FFRZVS principles of operation
The significant reductions in turn-on losses and higher efficiencies of FFRZVS are achieved by making small changes to the basic QR design. These changes are illustrated in Figure 2, which shows a FFRZVS reference design based on the Infineon XDPS21071 FFRZVS DCM controller.
Figure 2 The FFRZVS reference design is built around a flyback controller IC. Source: Infineon
An additional zero-voltage winding is added to the primary side of the circuit, alongside the primary winding and the auxiliary winding, which is used for zero-crossing detection. This zero-voltage winding, ZWVS, is added to the circuit, along with a capacitor, power switch, QZVS, and a low-side gate driver and RG1, enabling a self-controlled ZVS cycle.
Figure 3 The diagram shows the operational sequence of the FFRZVS design. Source: Infineon
When the primary MOSFET, QM, turns off at t0, there is a short blanking period before the synchronous rectifier, QSR, is turned on, causing current to flow in the secondary winding, WS. When this magnetizing current falls to zero, QSR is turned off, at t1, and the resonant circuit on the primary-side winding causes an oscillation around the voltage, Vbulk. At this point, t2, the ZVS MOSFET is turned on, bringing the additional winding, ZVS, into play. Switching on ZVS at the resonant peak of the primary MOSFET, where the magnetizing current is zero, results in a negative magnetizing current build-up.
Once this current reaches its peak at t3, the ZVS MOSFET is switched off again, causing the magnetizing current to reverse direction. This discharges the equivalent capacitance, resulting in the drain voltage of the primary MOSFET reaching a minimum at t4, where it turns on. Turning on at this point, where its drain-source voltage is minimum, leads to significant reduction in the turn-on losses, approaching those of true ZVS.
The above description highlights the important role that the controller plays in the implementation of FFRZVS, dictating the precision of the timing sequence, based on its measurement of the output voltage.
FFRZVS for USB PD adapters
A reference design for a USB PD adapter based on this operating principle is shown in Figure 4. The fixed-frequency ZVS controller used is specifically designed to target high-density power adapter applications. It is capable of operating in a number of modes, including discontinuous conduction mode (DCM), ZVS, frequency-reduction mode (FRM), and burst mode (BM), ensuring efficiency across different line and load conditions.
Figure 4 The reference design for a USB PD adapter is based on the FFRZVS operating principle. Source: Infineon
The digital and analog peripherals support various signal sampling and conditioning techniques, as required for flyback operation. A built-in high-voltage start-up cell makes the IC power supply much more efficient and flexible during no-load operation and high-voltage circuitry provides voltage monitoring as well as brown-in and brown-out protection.
Mode switching and timing control are handled by a nano-DSP with configurable, non-volatile OTP memory. This programmable capability enables a simplified PCB layout and reduced bill-of-materials.
Figure 5 The reference design achieves efficiencies greater than 90%. Source: Infineon
The reference design has also achieved a power-density of 15 W/in3 in a form factor of 55 (L) × 25 (W) × 25 (H) mm (Figure 5). The adapter has been proven to withstand worst-case 560V peaks on the primary side. In terms of heat generation, component temperatures do not exceed 100°C.
Emission tests conducted on this adapter have confirmed its compliance with EN 55022 (CISPR 22) class B test standards, thanks to the configurable frequency jittering, which helps improve the EMI signature at heavy loads and maximum switching frequencies. The adapter also fully meets standby power requirements; the 45 W design draws less than 30 mW of standby power at all AC input voltages. The design can also be easily augmented to support power output levels up to 65 W.
This article was originally published on EDN.
Wang Zan is senior staff engineer at Infineon Technologies.