Cadence expands collaboration with Arm to accelerate mobile device silicon success
Cadence has extended its collaboration with Arm to accelerate mobile device silicon success using its digital and verification tools and…
Synopsys, Arm strengthen partnership to advance next-gen mobile SoCs
Synopsys and Arm continue to deepen and broaden collaboration activities to accelerate time-to-market through highly optimized and silicon-ready system design…
Cadence PHY and controller IP in TSMC N7, N6 and N5 process nodes achieves PCIe 5.0 compliance
Cadence's PHY and Controller IP for PCIe 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed…
Synopsys unveils RF design flow for TSMC N6RF process
Synopsys' new RF design flow, developed with Ansys and Keysight for the TSMC N6RF process, boosts 5G SoC development productivity.
Four ways to build a CAD flow
The CAD flows for an IC design range from in-house development of custom tools to purchasing a customized tool built…
The pitfalls of mixing formal and simulation: Examples of the trouble
Three RTL DUT code examples illustrate the trouble that can occur when comparing the results from simulation and formal side-by-side.
The most common problem in functional verification
Blindly combining simulations and formal analysis can fool design engineers in believing that they have made a solid progress.
Synopsys and Analog Devices collaborate to accelerate power system design
Synopsys and Analog Devices are collaborating to provide model libraries for DC/DC ICs and µModule (micromodule) regulators with Synopsys’ simulation…
A look at the impact of Intel’s foundry foray on EDA, IP industries
Like IC design, the EDA and IP industries are an intrinsic part of the IC manufacturing ecosystem spearheaded by semiconductor…
Synopsys launches industry’s highest performance neural processor IP
Synopsys' new DesignWare ARC NPX6 NPU IP delivers up to 3,500 TOPS performance for automotive, consumer, and data center chip…