TSMC has certified Cadence's digital and custom/analog design flows for the latest N4P and N3E processes.
Siemens' Tessent Multi-die helps customers speed and simplify critical DFT tasks for next-gen ICs based on 2.5D and 3D architectures.
Cadence and Google Cloud are collaborating to accelerate system and semiconductor design with cloud-ready tools.
Here's why specifications are so important for formal verification.
As more systems companies move to design their own chips and electronic products, what are the key EDA trends impacting…
U.K. regulators have blocked the acquisition of EDA firm Pulsic by a Shanghai-based developer of semiconductor design software solutions.
With Cadence Liberate MX Trio, Arm achieved the accuracy and capacity required to address advanced-node memory characterization challenges.
Samsung Foundry achieves fast and accurate verification of its 3nm, 4nm and 5nm designs using the Cadence Spectre FX FastSPICE…
Here are some thoughts about a simple question: is analog EDA really an achievable thing? Blogger takes a closer look…
The Voltus-XFi Custom Power Integrity Solution delivers improved ease of use with minimal tuning and enables the development of efficient,…