The electronic system design (ESD) industry revenue increased by 12.1% YoY to $3.54 billion in Q1 2022, according to the ESD Alliance.
The 8nm RF design reference flow enhances time-to-results, quality-of-results and cost-of-results for next-generation RF design.
Cadence has expanded its Tensilica ConnX family with the debut of two new DSP IP cores for embedded processing in…
Cadence's Xcelium Apps enable automotive, mobile and hyperscale design teams to achieve the highest verification performance.
Cadence has extended its collaboration with Arm to accelerate mobile device silicon success using its digital and verification tools and…
Synopsys and Arm continue to deepen and broaden collaboration activities to accelerate time-to-market through highly optimized and silicon-ready system design…
Cadence's PHY and Controller IP for PCIe 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed…
Synopsys' new RF design flow, developed with Ansys and Keysight for the TSMC N6RF process, boosts 5G SoC development productivity.
The CAD flows for an IC design range from in-house development of custom tools to purchasing a customized tool built…
Three RTL DUT code examples illustrate the trouble that can occur when comparing the results from simulation and formal side-by-side.