A primer on engineering change order (ECO) using Conformal
Here is a detailed treatment of the premask flatten Cadence Conformal ECO flow that is widely used in the semiconductor…
Advanced verification: unlocking the door to a new era of AI chips
A look at how chip manufacturers will have to adjust hardware architecture in order to accommodate ever-growing demand for increased…
Cadence’s X factor
Cadence Sigrity X has been honored with the Best EDA Product of the Year award at the inaugural EE Awards…
What can analog EDA industry learn from word processor
EDA software needs to imbed intelligent decision making into analog design flow to enable engineers to focus on their designs…
A primer on logical equivalence checking (LEC) using Conformal
Logical equivalence check is an important phase in the IC design process where the design is evaluated without providing test…
Why scaling analog for power integrity analysis is critical
The EDA power integrity solution for the past 20 years has been post-layout SPICE simulation. That must change for bigger…
Power integrity tool caters to scale in digital and analog
Siemens Software's mPower provides EM and IR analysis for large analog and mixed-signal blocks.
Why power-aware signal integrity analysis matters in DDR5 design
DDR is used on many of the interfaces in computer systems, one of which relates to the way the processor…
Automated validation of multiple clock signals in SoC designs
The complexity in clocking subsystems in SoC designs is paving the way for automation to validate multiple combinations of clock…
Cloud the new frontier for EDA
Under the competitive pressures of the semiconductor industry, chip designers are choosing to migrate to cloud computing technologies.