2022-09-08 - Microchip Technology Inc.

Microchip rad-hard FPGAs achieve MIL-STD-883 Class B qualification

Microchip has now achieved the first qualification milestone with its RT PolarFire FPGA.

2022-07-07 - Microchip Technology Inc.

First RISC-V-based SoC FPGA enters mass production

The production qualification for Microchip MPFS250T and MPFS025T extends the PolarFire SoC portfolio of multi-core RISC-V SoC FPGAs.

2022-07-01 - Flex Logix Technologies Inc.

Flex Logix and CEVA unveil working silicon of DSP with embedded FPGA

The SOC2 was designed and taped out in a TSMC 16nm technology by Bar-Ilan University SoC Lab, as part of the…

2022-05-04 - Majeed Ahmad

eFPGA IP: Raising the SoC design game

Here is how the eFPGA technology is cashing in on the SoC design movement with a matrix of new possibilities…

2021-12-17 - Microchip Technology Inc.

Microchip launches second development tool for low-power PolarFire RISC-V SoC FPGA

Microchip has launched the second development tool offering in its Smart Embedded Vision initiative for designers using its PolarFire RISC-V SoC…

2021-09-23 - Majeed Ahmad

New tools streamline power system design around FPGAs

Tool makers are joining hands with FPGA suppliers like Xilinx to help designers simulate their power systems with accurate and…

2021-09-07 - Microchip Technology Inc.

Microchip strengthens FPGA platform with smart HLS tool suite

The smart HLS tool enhances accessibility to PolarFire FPGAs for hardware acceleration in edge compute systems.

2021-08-05 - Javier Valle and Adrian Helwig, Texas Instruments

Why radiation hardness matters for point-of-load converters

Space-qualified FPGAs bring with them challenging voltage regulation requirements.

2021-07-23 - Xilinx Inc.

Xilinx integrates stacked HBM to address bandwidth and security

New member of Xilinx Versal portfolio integrates stacked high bandwidth memory (HBM) to accelerate compute on massive connected data sets.

2021-06-18 - Deekshith Krishnegowda, Marvell Semiconductor

Avoid setup- or hold-time violations during clock domain crossing

To avoid data loss, designers need to ensure that setup- or hold-time violations don't occur during clock domain crossing.