2016-09-04 - Mufaddal Saifee & Jaymin Patel

Coding consideration for pipeline flip-flops

To achieve better performance, designs nowadays have their data pipelined through chains of flip-flops.

2016-09-04 - Mufaddal Saifee, Jaymin Patel

Making a reset usage strategy in ASIC/FPGA designs

The need for reset is governed by the system design and application, and various data and control paths are designed…

2016-08-23 - Rick Merritt

Intel to churn out Altera’s Stratix 10 by end of 2016

CEO Brian Kraznich promises “no changes in existing or planned products” using ARM cores.

2016-07-28 - Stephan Roche

Implement stepper-motor driver in CPLD

Here is a CPLD-based implementation of a stepper-motor driver that can also replace the driver in SAA1027- or UCN5804B-based designs.

2016-06-10 - Jeremy Willden

Testing FPGA’s thermal characteristics

By applying forward bias to parasitic diodes, you can smoke out those pesky thermal parameters.

2016-05-30 - Tews Technologies

Full mPCIe module packs user programmable FPGA

The TMPE633 from Tews Technologies is aimed at industrial, COTS and transportation applications, where specialised I/O or long-term availability is…

2016-05-24 - Stephan Roche

Add stepper-motor motion controller into CPLD/FPGA

Find out how a CPLD or FPGA can be a home for a stepper-motor motion controller and driver.

2016-05-16 - Stefaan Vanheesbeke

Swapping bits boosts performance of FPGA-PWM counter

A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a…