2022-06-20 - imec

imec demos backside power delivery with BPRs for back- and frontside routing

The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm…

2022-05-19 - Majeed Ahmad

TSMC targets conversion to 1.4-nm process node in June

TSMC plans to convert its 3-nm process R&D into a 1.4-nm process in June and thus reclaim sub-2-nm leadership from…

2022-05-05 - Majeed Ahmad

Apple lawsuit puts spotlight on SoC design engineering

Apple's lawsuit claims that Rivos has committed trade secret theft of its homegrown chip designs.

2022-04-22 - Majeed Ahmad

Disrupt or be disrupted: Intel and the great semiconductor fab game

Find out where Intel stands in its bid to compete with fab business behemoths TSMC and Samsung.

2022-04-12 - Maurizio Di Paolo Emilio

Deep silicon etch technology enables next-gen power devices

Lam Research's Syndion GP allows chipmakers to develop next-gen power devices and power management ICs using deep silicon etch technology.

2022-04-12 - Synopsys Inc.

Samsung Foundry adopts Synopsys and Ansys co-developed solution for advanced-node, energy-efficient chips

Samsung Foundry has achieved high silicon correlation with the jointly developed solution built on Synopsys PrimeTime signoff technology and Ansys…

2022-03-29 - Damian Bonicatto and Phoenix Bonicatto

Key options for analog debugging on bare-metal systems

Streaming data from firmware and displaying it on an oscilloscope can be a powerful tool and can speed up the…

2022-01-24 - Majeed Ahmad

Data converter IPs bolster presence in SoC designs

Data converter IP suppliers are cobbling strategic relationships with SoC designers while qualifying their offerings for foundry processes.

2022-01-19 - Omni Design Technologies

EnSilica and Omni Design partner on multiple SoC development

Omni Design and EnSilica will work together to service the needs of customers who are developing the next generation of…

2022-01-17 - Nitin Dahad

What is a system architect in SoC design?

With advanced chip design going into billions of gates on advanced nodes, dozens if not hundreds of engineers have to…