2020-04-20 - Jae Uk Lee, Dr. Ryoung-han Kim, IMEC, and David Abercrombie, Rehab Kotb Ali, Ahmed Hamed-Fatehy, Mentor

Multi-patterning strategies for navigating the sub-5 nm frontier, part 3

Determine the best self-aligned multi-patterning process solution for your advanced node applications.

2020-04-16 - Matthew Ballance

Reuse existing verification assets with the Portable Test and Stimulus Standard

How do we shorten our path to the rich rewards that PSS promises?

2020-01-27 - Rod Metcalfe

Machine learning in EDA accelerates the design cycle

IC designs keep growing in complexity, but AI and ML can shrink design cycles.

2020-01-10 - Vishwanath Tigadi

Macro models let engineers simulate circuits and systems

Mathematical models if circuits and systems give you a head start on developing your products before you're ready to build…

2020-01-01 - Frank Feng and Li Li

Automate ESD protection verification for complex ICs

Take an in-depth look at full-chip ESD protection verification, and how new automated verification tools and methodologies are helping to…

2019-12-20 - David Vincenzoni

Formal-based methodology cuts digital design IP verification time

Changing your methods of performing verification can reduce verification time by several weeks.

2019-10-31 - Rich Edelman

Getting in sync with UVM sequences

Writing sequences for the SystemVerilog UVM testbench is an essential, but often misunderstood, part of the design verification process.

2019-10-17 - Cherry Maskara

Get those clock domains in sync

With ICs and boards having many circuits, timing is critical. Multiple clock domains solve some timing problems, but you must…

2019-09-24 - Jae Uk Lee and Dr. Ryoung-han Kim, imec, David Abercrombie, Rehab Kotb Ali, and Ahmed Hamed-Fatehy, Mentor

Multi-patterning strategies for navigating the sub-5 nm frontier, part 1

In this first installment of a practical introduction to advanced multi-pattern semiconductor processes, we'll explore self-aligned double-patterning and self-aligned quadruple-patterning…

2019-09-12 - Maitry Ramesh

Parametric on-chip variation: A step towards accurate timing analysis

To accommodate more functionality on a single chip, the semiconductor industry is shrinking down the transistor technology at every node.…