From FinFET to GAA: Samsung’s fab journey to 3nm and 2nm
Samsung's development of the 3nm gate-all-around (GAA) process is on track and it has already made available the PDK in…
What’s driving the acquisitions in the analog design realm?
As chip designs combine sensors, analog and digital processing, chipmakers are maneuvering to add design capabilities for combined systems.
The state of analog design industry in 2021 and beyond
The recent flurry of mergers and acquisitions begs a simple question: what's happening in the analog and mixed-signal design realm?
A primer on logical equivalence checking (LEC) using Conformal
Logical equivalence check is an important phase in the IC design process where the design is evaluated without providing test…
Power integrity tool caters to scale in digital and analog
Siemens Software's mPower provides EM and IR analysis for large analog and mixed-signal blocks.
How to stop the antenna effect from destroying your circuit
Besides the complete failure of devices due to the antenna effect, analog designers are also worried about its impact on…
ParagonX: Profile of a debugging tool for analog designs
As the industry migrates to FinFET technologies, IC layout parasitics has become the dominant source of bottlenecks in mixed-signal SoCs.
Renesas enhances Lab on the Cloud environment
Renesas has expanded its popular Lab on the Cloud environment to simplify the configuration and testing process and speed time…
Analog layout: Why wells, taps, and guard rings are crucial
Here are the key examples of well, taps and guard rings, and why these structures are essential to the layout…
Enabling industrial-grade open verification for RISC-V
Here's a look at an open-source IP with industrial-grade verification and open methodology to support verification of an open-source CV32E40P…