Enabling industrial-grade open verification for RISC-V
Here's a look at an open-source IP with industrial-grade verification and open methodology to support verification of an open-source CV32E40P…
Configurable analog IP supplier joins the RISC-V fray
RISC-V International has accepted Agile Analog as a strategic member and that underscores critical role of analog building blocks in…
RISC-V speaks on options after Nvidia-Arm news
As the embedded industry digests the implications of the proposed acquisition of Arm by Nvidia, RISC-V International, the organization supporting…
A guide to accelerating applications with just-right RISC-V custom instructions
With RISC-V, standard extensions can be used to configure the base processor...
Drag and drop with new software and IP for processor-based FPGA design
A new design environment to empower developers of any skill level to quickly design FPGA-based applications using a drag-and drop…
How to make processors trustworthy?
The RISC-V assurance process presented in this article detects scenarios that could affect security, and systematically unveils undocumented functions and…
RISC-V Foundation clears up Princeton’s ‘100 errors’
A single change to the RISC-V instruction set architecture specification may eliminate the failures, according to the foundation.