Cadence design flows support TSMC 3Dblox
Cadence's new design flows support the TSMC 3Dblox standard for 3D front-end design partitioning in complex systems.
EDA toolmakers prep for TSMC’s N3E and N2 nodes
The trio of large EDA houses are onboard and here is a synopsis of their undertakings to prepare for the…
TSMC adds two variants to 2nm node; will Intel catch up?
Taiwan's mega-fab will add two variants to its N2 technology in 2026: N2P with backside power delivery and N2X for…
TSMC upends 3nm roadmap with three new nodes
The mega-fab's 2023 North America Technology Symposium has provided ample information on the latest 3-nm nodes: N3P, N3X and N3AE.
Cadence collaborates with TSMC on 79GHz mmWave design reference flow on N16 process
Cadence has collaborated with TSMC to optimize its Virtuoso platform for the 79GHz mmWave design reference flow on TSMC's N16…
What Arm’s Prototype Chips Mean for the IC Industry
Arm is building prototype chips to demonstrate the power and capabilities of its IPs and designs to the wider market.
Synopsys Strengthens Collaboration with TSMC and Ansys to Advance Multi-Die Systems
The close collaboration addresses chip, package and system-level effects for designs on TSMC advanced technologies.
TSMC’s 3-nm progress report: Better than expected
Taiwan's mega-fab has successfully launched 3-nm process node and its yield is reportedly around 80% for early chips produced for…
2D material breakthrough brings TSMC closer to 1nm
TSMC is setting up a new 1-nm chip production facility that will be located in an industrial park in Longtan…
Cadence design flows now certified for TSMC’s latest N4P and N3E processes
TSMC has certified Cadence's digital and custom/analog design flows for the latest N4P and N3E processes.