When Flash is external to the SoC, memory is no longer a limiting factor. Developers can select a best-in-class SoC based on its performance and scale Flash density independently. Being able to right-size Flash memory also reduces system cost and footprint.
For decades, the prevailing strategy for innovating electronic system design, regardless of industry, has been to integrate more capabilities and greater memory capacity into fewer chips. This has led to the rise of complete system-on-chip (SoC) architectures, enabling complex embedded systems to be designed around a single chip. Complementing integration has been increasingly tighter manufacturing process nodes and shrinking die size. The result is smaller SoCs capable of higher performance at a lower cost.
The increased capabilities enabled by integration at the chip level has led to the consolidation of features and capabilities at system level. For example, in today’s evolving autonomous vehicle architectures, instead of comprising several distinct subsystems in a distributed architecture, functionality is now being consolidated into a single vehicle control platform (VCP). These platforms offer greater efficiency, control, and reliability, as well as optimized power management and overall reduced system footprint and weight.
Centralized computing is possible through the increased compute power of integrated SoC architectures. And, as vehicles become more intelligent, they require greater processing resources within the vehicle. In fact, cars are going to need significantly more intelligence – and data storage – to move to the next level of autonomy.
Embedded NOR Flash has made it possible to execute code directly from Flash. To achieve the power and performance requirements, compute-intensive applications like autonomous vehicles need SoCs manufactured at the smallest reasonable process node. The integration strategy, however, has begun to fall short as manufacturing process nodes shrink to 22nm and below. Specifically, embedded NOR Flash has become prohibitively expensive to implement at these smaller nodes.
Thus, systems using high-performance SoCs need an alternative to embedded Flash, namely returning to the use of an external memory device.
De-integrating embedded Flash
For highly integrated SoCs to maintain real-time performance, external Flash needs to have minimal negative impact on data throughput, code execution, reliability, and security. The surprising truth is that moving Flash off-chip offers significant scaling and flexibility benefits as well.
Traditionally, an external memory bus is slower than an internal bus, so moving off chip requires an enhanced architecture that avoids introducing memory throughput bottlenecks. Specifically, such an architecture needs to be optimized for read time and system startup.
Fast read time/throughput enables execute-in-place (XiP), where code runs directly from Flash. Any slower and the Flash will become a processing bottleneck. As systems such as autonomous vehicles continue to consolidate more and more functionality, fast system startup of these consolidatd systems becomes more challenging as well.
Recognizing this, Infineon’s research and development teams are evaluating architectures designed to deliver internal memory read performance from an external memory (see Figure 1). These new designs achieve sufficient read performance by utilizing an optimized LPDDR4 interface with an extreme bandwidth of greater than 3200 MBps. This level of performance delivers 10X the bandwidth of conventional external NOR Flash. Combined with a fast initial read latency of less than 20 ns, this advanced Flash is more than fast enough to support code execution from external Flash.
The new memory achieves this level of optimization by leveraging the fact that code is written once (i.e., storage of code) and read many, many times (i.e., execution of code). Given that XiP performance is based on read operations only, the optimized LPDDR4 interface avoids delays from write initializations of the bus.
NOR Flash plays an important role in keeping complex systems like autonomous vehicles flexible by enabling remote updates even after systems are deployed. With over-the-air (OTA) update support, new features can be added to vehicles even after they are on the road.
Offering a Flash device with multiple different banks inside the memory enables the architecture to support read while write (RWW) functionality where the system can load new code without having to interrupt overall system operation (i.e., zero downtime).
Reliability and safety
Automotive applications, by their nature, require higher reliability and must employ functional safety capabilities to prevent damage to equipment and avoid injury to people. The basic level of safety required is “fail safe”, where the system can safely shut down when a failure occurs.
A vehicle traveling at 60 mph, however, cannot afford to fail, even safely. The system must be “fail operational”, meaning that users can still use basic functionality to bring the system to a safe state (i.e., braking to safely slow the vehicle). At Infineon, we are pushing processor and memory technology to exceed fail operational standards and achieve “High Availability” where systems are designed to detect, identify, and mitigate potential failures with zero downtime.
Dependable memory is essential to assuring these higher levels of safety. External NOR Flash must comply with the appropriate safety standards (i.e., ISO 26262). They also need to comply with application standards such as the AEC-Q100 automotive standard.
One of the roles Flash plays in assuring safe operation is through safe boot, where memory recovers from a power event in a known good state that is at least fail operational.
With the ability to perform OTA updates comes the need to protect code and firmware with sufficient security. Ideally, data is secured where it resides, not in the processor. Storing code in external memory introduces the need to secure the memory interface as well.
Companies are already tackling the problem of integrating advanced security into external Flash memory devices. For example, Infineon SEMPER Secure implements a hardware-based root of trust to assure that the system boots from a safe, known-secured state and prevents any unauthorized access or modification to the code in the external memory.
Benefits of de-integration
The de-integration of Flash actually provides developers with greater scalability and flexibility. When embedded Flash is integrated into an SoC, Flash density has been optimized and balanced based on the performance requirements of the entire system as well as available die area. If there is not enough Flash, the processor will not be useable for certain applications. Alternatively, if there is too much Flash, this impacts system cost. Embedded Flash density can significantly limit processor selection choice, forcing developers to choose from a short list of options, none of which is ideal.
When Flash is external to the SoC, memory is no longer a limiting factor when selecting the optimal SoC for an application. Developers can select a best-in-class SoC based on its performance and scale Flash density independently. Being able to right-size Flash memory also reduces system cost and footprint.
Flexibility on memory density has other benefits. Products in a line can have different processing and program memory capabilities to match increasing feature sets across the line. For example, an ADAS system requires varying amounts of memory depending upon the capabilities enabled.
New powertrain architectures for hybrid and electric vehicles require sustainable solutions that deliver optimal performance, functional safety compliance (ISO 26262), power management, remote update, and self-diagnostic capabilities. The industry is developing embedded Flash replacements for automotive systems and other high-performance applications.
It may seem counterintuitive to de-integrate Flash after all the work that’s gone into integrating it into the processor. However, it’s an architectural transition nearly every industry using high-performance processors is going to have to make. The good news for OEMs is that all the reasons to integrate memory onto the processor – faster throughput, lower power consumption, enhanced security, greater reliability, ease of design – can now be delivered by external Flash.
This article was originally published on Embedded.
Sandeep Krishnegowda is senior director of marketing and applications for the Flash business unit at Infineon Technologies. He has over 15 years in experience in a variety of engineering, management roles. He earned an MS in electronics from Rensselaer Polytechnic Institute and a BE in electronics and communication from Visvesvaraya Technological University.