Surprise at what appeared to be a flaw in the design of the NE555 led to an interesting experiment and to the even more interesting history surrounding the chip and its designers.
We’ll start with my power supply. It’s a 143D two amp bench supply from Southwest Technical Products Corporation . It came as a kit, and I built it around 1968. Although admittedly the caps are likely in poor shape, it has worked well for various projects over the years.
Despite its popularity, I had never used an NE555. For doing some recent experiments, I purchased several. I mainly foresaw the need for an oscillator here and there, and this looked like an easy way to get one when required.
However, when I tried one out, using my good-old 143D power supply, I was in for a surprise. The power supply went crazy, overcurrents pinning the meter, and so forth. It’s tough and this did not kill it (however nor did it made it stronger). I wondered what was going on, but at that point I was in the midst of some other circuit work, so I put the parts aside.
Recently, I got a new power supply, a Siglent SPD3303X. It was about time! I decided to try the NE555 again, and while this time it did not bring the power supply to its knees, I discovered more about what turns out to be a notorious problem.
The issue is well-documented. At first I didn’t know what to make of it, as it seemed to be a serious design flaw: Totem-pole outputs, connected directly to the positive rail and ground, without any kind of current limiting or special switch timing, that allows both transistors to be on very briefly, drawing large currents. I have worked a lot with TTL, discrete transistors of various types, opamps, various more complex chips, even relays, and had never encountered a spike this severe, even with my old power supply.
Various people have posted scope traces and described the issue [3,4,5,6,11,14,15]. Typical reports are of a current spike that lasts 100-200 nsec and pulls about 300 mA. This is more than 10 times the normal unloaded current drawn by the chip. With no decoupling capacitors, power supply drops can be seen of more than half the supply voltage. My case is no different; the Siglent SPD3303X has excellent specs, and I can see these kinds of voltage drops.
I did some experiments as well and the results are below. But more importantly, as I delved further into it, I found that this chip has a fascinating history.
Hans Camenzind designed the NE555 in the two or so years before its release in 1972 by Signetics. In Jack Ward’s An Interview with Hans Camenzind , he tells of the trials of getting the design established, issues with his employer (he wound up doing it under contract, very unusual in those days), and of the courage and conviction of Art Fury, Signetics’ marketing manager, in pushing the product through.
Camenzind notes in the Interview that his design was subjected to internal reviews. Certainly the output stage was an important topic. Similar ICs at the time, such as TTL gates, tried to reduce the power spikes using current-limiting resistors, diodes, and timing. But one of the goals of the NE555 was that it should be able to drive a fairly large load. So the decision to make the totem-pole output directly connected to Vcc and ground was probably deliberate.
While it’s not clear when the power supply spike issue was recognized, Camenzind realized early on that the original design had shortcomings. His article, Redesigning the old 555, from IEEE Spectrum in 1997 , and the subsequent description of the 555 Second Version in his Designing Analog Chips (2005) , together enumerate the flaws and describe improvements: Better bias circuits to reduce sensitivity to power supply variations and expand supply voltage range; balanced active loads added to the comparators to enhance accuracy and speed; a new low-current, current-mode flip-flop to reduce switching time. Major overall goals were to reduce operating current and lower the required supply voltage; these also had significant implications for the output stage.
The schematics of all three devices are shown below in Figures 1-3. Note that the later designs take advantage of the greater density available by then.
The output stage is a prominent topic in both the Spectrum article and Designing Analog Chips. Camenzind went so far as to say in the latter that “the most significant change is in the output stage”. The Spectrum article also mentions that the Zetex ZSCT1555 is available as the redesigned 555, presumably following the concepts described in the article. However in the later Designing Analog Chips it’s not clear that the output current requirements have in fact been established: Camenzind mentions the large-current source and sink of the original 555, and shows a totem-pole output in the 555 Second Version, but there is no explicit statement of the output current requirements for the new chip. He does describe various enhancements to control currents and timing, such that he claims the current spike is eliminated.
On the other hand the ZSCT1555 design reflects much of what was described in Spectrum. Both that and the 555 Second Version use the “Widlar Latch” positive-feedback loop. In the 555 Second Version, this comprises Q40, Q41, and Q42. The ZSCT1555 is clearly oriented toward lower-power and lower-voltage use. Note for instance that the minimum supply voltage is lower, and the output current specs are asymmetrical: It can sink 100 mA, half of that of the NE555, but can only source 150 µA. However the maximum speed is also less than that of the NE555. Using a PNP collector-drive output transistor for the high side is appropriate for a low-current high, and Camenzind explicitly mentions supporting large currents only as a sink in the Spectrum article. And since the high side does not draw much, we can see that would eliminate current spikes.
Despite Camenzind’s clear writing and unabashed openness, the original 555 design is still the one on the market. The CMOS version appears to have filled some of the market gaps for low-power. But efforts at producing a “better” bipolar 555 have all succumbed to the overwhelming force of the original.
Figure 1 Original 555 timer, from the Signetics Analog Applications Manual .
Figure 2 Hans Camenzind’s 555 Second Version, from Designing Analog Chips .
Figure 3 Zetex ZSCT1555, a pin-compatible, lower-power version of the 555, from the spec sheet .
My own experiment with the NE555 is displayed in Figure 4 below. The compact layout produces reasonably clean signals. All of the components shown in the schematic except the power supply are on the circuit board. 437 mA peak draw is fairly hefty, and this comports with other reports.
Some of my other recent experiments involve three individually-tunable, free-running oscillators, whose frequencies may be reasonably close to each other. To avoid having the current spike propagate spurious synchronizing signals among the timers, I wound up heavily filtering the power supply at each chip with a suitable resistor and electrolytic capacitor. Although this dropped the usable supply voltage, it was enough to drive the downstream components. But it’s unfortunate that more components need to be added than functionally required to compensate for the issue.
Figure 4 NE555 test setup: schematic, scope traces, and layout.
The 555 Second Version was never built. The ZSCT1555 has been discontinued. But the NE555, after fifty years—and ten years after Hans Camenzind left us—is alive and well, reported by some to be the most popular chip in history.
It is, I suppose, an engineer’s virtue as well as an engineer’s curse to feel so strongly the pull to fix some aspect of a design after it’s left the building. Hans was clearly a designer who was not only very creative but also highly disciplined and who put enormous up-front thought into his designs. The issues surrounding the original 555 must have bothered him; in the Interview he said that he was “stunned” that improvements to the 555 didn’t catch on. In the end, his creation had a will of its own.
I’m sure we can all think of similar cases—though perhaps not on the scale of that of Hans Camenzind. Any design is subject to “be careful what you wish for…” If it fails, you lament for a moment and try again. If it succeeds, you need to keep in mind that it may be very difficult to get those horses back in the barn.
This article was originally published on EDN.