RF SiPs and heterogeneous integrated circuits (HICs) are emerging as venues for creating highly compact assemblies for wireless applications.
RF communication and sensing systems are becoming incredibly complex. This has been an ongoing trend as wireless communication and sensing technology adoption has continually evolved, while reliance on these technologies in virtually all human activities is on the rise. From warfare to healthcare, wireless communication and sensing technologies are often a key component of the latest solutions and are seen as necessary to stay competitive in the marketplace or in the battlefield.
There are a few enabling factors for this rise, namely advances in high-speed signal processing, FPGAs, ASICs, memory, storage, and communication interfaces that can handle an immense amounts of data throughput while using advanced antenna systems (AAS). The multi-input multi-output (MIMO) and beamforming systems themselves require substantial amounts of processing, but that data must also be transferred to and from the RF front-end (RFFE) and antenna processors to compute resources, data storage, and possibly even to IT infrastructure.
Below is an outline of the key components serving modern wireless communication and sensing systems:
1. RF front-end hardware
2. Processing and converting hardware
Central processing units (CPUs)
Graphics processing units (GPUs)
Field programmable gate arrays (FPGAs)
Application specific integrated circuits (ASICs)
Digital signal processors (DSPs)
Machine learning/artificial intelligence cores
Analog-to-digital converters (ADCs)
Digital-to-analog converters (DACs)
3. Accessory hardware
Interconnect design challenges
The interconnect necessary to handle the level of throughput for current mmWave 5G devices, active electronically scanned arrays (AESAs), and the like is already extremely complex and requires major design considerations and substantial board space to ensure high levels of signal integrity. Future 5G and 6G communications as well as emerging advanced wireless sensing technologies are only pushing these throughput and processing requirements even further.
Current technologies for processing and data transport are typically co-located on PCBs on closely assembled modules that use high-speed and high-density board-to-board interconnects. For some current applications and future applications, this arrangement requires far too much space, which results in substantially inefficiencies and leads to electromagnetic interference (EMI) issues.
A possible solution to some of these challenges, albeit at the trade-off of increased fabrication complexity, is to integrate all the necessary RF, processing, storage, memory, and communication interfaces into a single package: systems-in-package (SiP), or even on the same chip, systems-on-chip (SoC). However, integrating high-performance RF hardware using a single fabrication process is still likely several years from reaching the market.
That’s because integrating complementary metal-oxide semiconductor (CMOS) technology alongside class III-V semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP) presents significant challenges. Still, the current fabrication and assembly technologies are going through some significant development to create extremely compact assemblies within a single package, heterogeneous integrated circuit (HIC).
RF SiP and HIC solutions
These RF SiPs (RFSiPs) can either be stacked as true 3D SiPs, offset-stacked in 2.5D SiPs, or placed on the same real estate as 2D SiPs. Typically, wire bonding is used to provide interconnect directly from die to die, though other interconnect methods, such as vias, are being developed and are used in some more recent silicon-based technologies. RF SiPs currently range from just two or more co-packaged devices, such as a mixer and amplifier, to what Mercury Systems is calling an adaptive compute acceleration platform (ACAP) and network-on-chip technology.
HiCs have been around for several years in the computer hardware industry as a way of packing more processing, storage, or memory technology into a smaller and more energy-efficient package. Adding RF hardware into these packages adds yet another level of complexity. This is likely why there has been substantial investment from the Defense Advanced Research Projects Agency (DARPA) and collaborations among various OEMs and semiconductor fabricators to realize viable methods of integrating the individual chiplets that comprise an RF SiP.
Stay tuned for my next RF blog for the rest of this discussion.
This article was originally published on Planet Analog.
Jean-Jaques (JJ) DeLisle, an electrical engineering graduate (MS) from Rochester Institute of Technology, has a diverse background in analog and RF R&D, as well as technical writing/editing for design engineering publications. He writes about analog and RF for Planet Analog.