Three ways of looking at a sigma-delta ADC device
Article By : Vladyslav Kozlov
The article presents three major design considerations for a ΣΔ analog-to-digital converter (ADC): basics, structure, and accuracy.
The growing availability of digital ICs like microcontrollers, microprocessors, and field-programmable gate arrays (FPGAs) allows developers to use complex digital processing techniques rather than analog signal conditioning. For this reason, analog-to-digital converters (ADCs) have become a widely-used component in mixed-signal circuits.
There are many types of ADCs: successive-approximation ADCs, sigma-delta (ΣΔ) ADCs, direct-conversion ADCs, capacitor charge/discharge-based ADCs, ADCs with voltage-to-frequency converters, and others. All these ADCs provide different accuracy characteristics, sampling rate limitations, and cost points.
This article outlines three major design considerations for selecting a ΣΔ ADC.
- Sigma-delta ADC basics
The main components of a first-order ΣΔ ADC are:
- Integrator
- Comparator
- 1-bit digital-to-analog converter (DAC)
- Digital filter
The simplified schematic of a first-order ΣΔ ADC is shown in Figure 1.
Figure 1 The schematic shows the basic building blocks of a ΣΔ ADC. Source: Renesas
The operating principle of a ΣΔ ADC is based on the periodic balancing of the charge of the integrator’s capacitor. The integrator changes its output linearly until it crosses a threshold. When the threshold is crossed, the comparator changes the state of a 1-bit DAC to the opposite state. This forces the integrator to change its output in the opposite direction—up or down depending on the DAC output. The process then repeats. The comparator must change the DAC state synchronously using external clock pulses (Figure 2).
Figure 2 The ΣΔ ADC waveforms for (A) amount to Vin= Vdd/2 and for (B) Vin=Vdd*3/4. Source: Renesas
The ΣΔ ADC can be treated as a low-resolution ADC during one integrator period. To get a high-resolution result, the data from several periods must be averaged. This inherent oversampling and averaging allows the ΣΔ ADC to greatly minimize noise and get high-resolution data—up to 24 noise-free bits for modern ΣΔ ADCs.
The bitstream—the output of the synchronous comparator—is input to a digital filter. The typical filter is a moving average low pass sinc1, sinc3, or sinc5 filter.
- The ΣΔ ADC structure
The simplified structure of a configurable mixed-signal IC is shown in Figure 3. An integrator based on Opamp0 adds the input signal and the signal from the 1-bit DAC. The reference voltage for the integrator and the comparator is Vdd/2. Note that the digital rheostat divider can be used instead of the internal VddA/2 reference to compensate for the offset of Opamp0 (Figure 4). The ADC reference voltage is ADC_Vref=Vdd=VddA.
Figure 3 Simplified structure of the ΣΔ ADC is based on the SLG47004 configurable mixed-signal IC. Source: Renesas
The 1-bit DAC is a GPIO configured as a 1x push-pull output pin. The 16-bit counter operates as an accumulator that counts the number of clock pulses wherein the analog comparator (ACMP) output is high. The counting period for the 16-bit counter is 65536 pulses of the oscillator. A low-level Power Up signal turns off Opamp0, ACMP, and the oscillator. This significantly reduces the power consumption of the SLG47004 when the ADC isn’t used.
Figure 4 The optional connection of digital rheostats adjust the reference voltage of Opamp0. Source: Renesas
The ADC result is stored in the current counter value registers of 16-bit CNT0 (register bytes CBh, CCh). The result can be read via an I2C interface.
If the Power Up input is high, the rising edge at the Start Conversion input starts the sampling procedure. The InProgress/Idle output can be monitored to define the end of the conversion. To start a new sampling procedure, the rising edge should be reapplied to the Start Conversion input. The sampling rate of the ADC is 1.95 samples per second.
A high-level view of the GreenPAK Designer Software project built around the ΣΔ ADC is shown in Figure 5.
Figure 5 The ΣΔ ADC in the GreenPAK Designer project is based on SLG47004 configurable mixed-signal IC. Source: Renesas
The hardware prototype waveforms are shown in Figure 6.
Figure 6 Hardware prototype waveforms for Vin=1.0 V amount to ADC_Vref=Vdd=3.0 V. Source: Renesas
- Accuracy characteristics
To estimate the accuracy characteristics of the ADC, an external 24-bit ΣΔ ADC was used. The external ADC was configured to operate in 16-bit mode at 1 ksps, averaging 128 samples. The SLG47004 and external ADC used the same voltage reverence of 3 V. For the SLG47004, Vdd=VddA=ADC_Vref. The SLG47004 uses the rheostat divider to provide a reference to Opamp0. The code for both digital rheostats is 1023.
Table 1, Table 2, and Figure 7 show the comparison results.
Table 1 The data shows the comparison of results of external Etalon ADC and SLG47004-based ΣΔ ADC. Source: Renesas
Table 2 The data highlights the linearity assessment of the SLG47004-based ΣΔ ADC. Source: Renesas
Figure 7 The graph highlights the comparison of Etalon ADC with SLG47004-based ΣΔ ADC. Source: Renesas
The SLG47004-based ΣΔ ADC demonstrates robust linearity (1.7 LSB max), good noise tolerance (the result deviation is 2 LSB over a sequence of samples), and small gain error (0.009% of full scale) and offset error (0.5 mV). It’s worth noting that the SLG47004-based ADC isn’t calibrated, so the performance of the ADC can vary from chip to chip and can be worse than shown above. To improve the performance, the rheostat divider (Opamp0 Vref source) can be used (Figure 4). The calibration procedure is an adjustment of Opamp0’s Vref divider output to minimize the difference between the SLG47004 data and the Etalon ADC data when the input voltage is Vin=ADC_Vref/2.
The proposed ΣΔ ADC can be used as a standalone 16-bit ADC or combined with other analog designs inside the SLG47004 mixed-signal IC. The internal resources needed to implement the ADC are one op amp, one ACMP, one GPIO, and a few logic components clocked by an oscillator. The proposed ΣΔ ADC has a low sampling rate (1.95 sps) but good accuracy characteristics (0.5 mV offset error, 0.009% gain error, and 2 LSB max INL) and good noise immunity. The user can optionally select a higher sampling rate at the expense of accuracy.
This article was originally published on Planet Analog.
Vladyslav Kozlov is team lead for product development engineering at Dialog Semiconductor, a Renesas company.