There have been ongoing efforts to develop solutions to the limitation of CMOS FET technology, including negative capacitance FETs (NC-FETs).
It has been long known that complementary metal-oxide semiconductor (CMOS) transistors suffer from a scaling issue. As CMOS field-effect transistors (FETs) get smaller, they become less power efficient, and in turn, vulnerable to self-heat to a greater degree. This becomes an issue when the heating due to power dissipation becomes so great that the CMOS-FET device cannot operate efficiently. This concept is known as Boltzmann’s Tyranny, which is defined by the thermionic limit of the MOSFET’s subthreshold slope (SS) at 60 mV/dec at 300k. This phenomenon results in a lower limit to the operating voltage, which ultimately limits the power dissipation of a standard FET.
As this limitation of CMOS FET technology is known, there have been ongoing efforts to develop solutions to this problem. Some examples of these potential solutions include tunnel FETs, spin FETs, nano-electromechanical FETs, phase FETs, and more recently, negative capacitance FETs (NC-FETs). As proposed in the technical paper titled “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices,” NC-FETs are designed with the standard insulator replaced by ferroelectric insulators of a specified thickness.
This solution can create a step-up voltage transformer that increases the gate voltage, and leads to lower values of SS than 60 mV/dec. Such a solution allows for lower voltage FET operation, which coincides with lower power dissipation and greater device efficiency. This proposed solution, as originally delivered, doesn’t involve any intrinsic changes in the physical operation of an FET, and merely enables the on-current threshold to be reached at a lower supply voltage.
Figure 1 The above diagram demonstrates stability and feasibility of ferroelectric-based NC-FETs. Source: Springer Nature
However simple the theory of an NC-FET is, the reality of developing and modeling these devices has been far less simple since 2008, when the NC-FET was originally proposed. It appears that one of the main reasons for this is that the originally-proposed NC-FET requires that the negative capacitance state of the ferroelectric insulator is stabilized in the single domain state, the quasi-static NC model. Unlike ferroelectric FETs (Fe-FETs), which have hysteretic I-V characteristics, an NC-FET doesn’t exhibit this (Figure 2).
Figure 2 An NC-FET adds a thin layer of ferroelectric (FE) material to the existing gate oxide of a MOSFET. Source: AIP Publishing
Moreover, with the NC-FET, the total gate capacitance is still positive, whereas in an Fe-FET, the total gate capacitance is negative. In essence, an NC-FET requires that the I-V characteristic is sweep-frequency and sweep-voltage independent and hysteresis-free.
A challenge in NC-FET design is that a too-thick ferroelectric (FE) layer can lead to negative differential resistance (NDR), which likely degrades NC-FET device performance. This is due to greater thicknesses of FE material allowing for higher interface electric field strength with a greater interface/bulk traps. These NDR effects also lead to hysteresis of the device, and must be addressed for the future development of NC-FETs. Fortunately, true NC-FETs also exhibit drain induced barrier rising (DIBR), which actually leads to a decrease in the off current, a benefit to the low supply voltage operation of an NC-FET.
What remains is development of CMOS-compatible processes for fabricating NC-FETs, NC-FET technologies that are stable and reversible, and NC-FETs that can be scaled to 2.5nm to 5nm process nodes.
This article was originally published on Planet Analog.
Jean-Jaques (JJ) DeLisle, an electrical engineering graduate (MS) from Rochester Institute of Technology, has a diverse background in analog and RF R&D, as well as technical writing/editing for design engineering publications. He writes about analog and RF for Planet Analog.