Understanding the benefits of pre-charge buffers in ADCs

Article By : Keith Nicholas

Here is how pre-charge buffers benefit both analog input path and reference input path in high-performance analog-to-digital converters.

One of the goals for designers of new high-performance analog-to-digital converters (ADCs) is to relax the design requirements for the external input amplifier and reference, often by including integrated buffers for both the analog and reference inputs. For high-performance ADCs, however, adding any components to the signal chain can degrade overall device performance.

Design priorities include choosing the silicon process, circuit design, layout and IC packaging to optimize the voltage offset, gain, signal-to-noise ratio (SNR) and total harmonic distortion (THD), among other specifications. The addition of a traditional buffer can affect these specifications, and many times, these buffers become the dominant source of error in a high-performance ADC. One alternative to a traditional buffer is a pre-charge buffer, as shown in Figure 1. This article will focus on the use and benefits of pre-charge buffers in both the analog input path and the reference input path.

Figure 1 This is how pre-charge buffers complement the 24-bit, 400-KSPS ADS127L11 wideband delta-sigma ADC. Source: Texas Instruments

One way to simplify input amplifier drive requirements is to use a charge bucket filter at the ADC inputs, where the differential capacitor is large compared to the internal sampling capacitor. This simple resistor-capacitor network, denoted in Figure 2 as R_filt and C_filt, acts as a charge reservoir to supply most of the instantaneous current required by the input sampling capacitor, C_in. The external filter capacitor C_filt reduces the peak input current from relatively high current pulses on the order of tens of milliamperes to less than 1-mA peak, with an average current of hundreds of microamperes.

Using a large external input capacitor to reduce the peak currents also reduces the high bandwidth requirements of the input amplifier, providing a wider range of amplifier choices. These additional amplifier options allow the designer to optimize for low power, DC performance, and a number of other design criteria.

One drawback with using a large external input capacitor, however, is that it limits the maximum input signal frequency. It’s a first-order low-pass resistor-capacitor RC filter. Another drawback is that the capacitor impedance becomes very low at higher input frequencies, resulting in high current flowing through the capacitor. This high current from the input amplifier results in increased power dissipation in the system, which can be excessive for high-density or battery-powered systems.

Many low-power precision amplifiers may not be able to support high currents and preserve good SNR and THD. Using a large input filter capacitor may be an acceptable approach for very low-frequency input signals or DC inputs, but for input frequencies of 10 kHz or higher, the load current and resulting power dissipation can become unacceptably high.

Design flexibility with pre-charge buffers

Another option that relaxes input amplifier drive requirements and does not reduce total ADC accuracy is a pre-charge buffer. Pre-charge buffers are specialized amplifiers that charge the internal sampling capacitor of the ADC during the first part of the acquisition cycle and then disconnect in the second half of the acquisition cycle to enable a direct connection between the ADC inputs and the internal sampling capacitor. Directly connecting the internal sampling capacitor to the inputs during the final part of the acquisition phase removes any errors in the pre-charge buffer from the signal path. The use of the pre-charge buffer reduces the overall dynamic load on the external input amplifier by more than 99%.

Another benefit of a pre-charge buffer is lower THD when used in combination with a high-bandwidth external input amplifier. Using a pre-charge buffer in addition to a high-speed input amplifier can improve total THD by 10 dB or more. The trade-off is additional power consumption—since both the high-speed amplifier and internal pre-charge buffers are enabled—against the flexibility to prioritize lower distortion or lower power.

Figure 2 Fully differential input amplifier with internal pre-charge buffer is shown in a typical high-level signal chain. Source: Texas Instruments

The main drawback of a pre-charge buffer is the small dynamic current needed to finish charging the internal sampling capacitor in the second half of the acquisition phase. However, this dynamic current is less than 1% of the current required to directly drive the input sampling capacitor without enabling the pre-charge buffer. And it enables the use of much lower bandwidth amplifiers and a smaller input filter capacitance.

While Figure 2 shows a typical high-level signal chain, with the external input amplifier and internal pre-charge buffers used to charge C_in, Figure 3 highlights the timing details for the pre-charge buffer.

Figure 3 Input sampling capacitor voltage (V_cin) is shown during coarse and fine acquisition phases. Source: Texas Instruments

AIN-Coarse, AIN-Fine and AIN-Reset are the internal switch control signals. The internal switch is on with a control level of 1 and off with a control level of 0. Looking at the V_cin waveform, the voltage across the internal sample-and-hold capacitor, you can see how the pre-charge buffers charge the input capacitor voltage to about 99.9% of the final target value, or 3.98 V during the AIN-Coarse = 1 phase. The external input amplifier only needs to charge the internal sampling capacitor during the AIN-Fine = 1 phase to a final input voltage of 4 V.

How pre-charge buffers optimize input current

As discussed earlier, the pre-charge buffer reduces the average input current needed to drive the inputs. It is possible to derive an equation for average input current with the pre-charge buffers enabled, but let’s first derive an equation for the average input current without the pre-charge buffers when directly driving the inputs. Equation 1, for the average input current, is based on the familiar equation for total charge in a capacitor:

Q_in = C_in × V_in                     (1)

Where Q_in is the total charge on the C_in and V_in is the voltage of the sampling capacitor at the end of the acquisition period, which is approximately equal to the voltage on the ADC inputs.

Since the sampling capacitor is reset to 0 V at the end of the conversion phase, you can represent the average input current as shown in Equation 2:

I_avg = Q_in × F_mod                  (2)

Where F_mod is the modulator sampling rate or the sampling frequency at the ADC input.

In the case of the ADS127L11 delta-sigma ADC, the modulator sampling rate is equal to one-half the main clock frequency, F_clk, when using high-speed mode. Substituting Equations 3 and 4 into Equation 2 results in Equation 5:

Q_in = C_in × V_in                                   (3)

F_mod = ½ × F_clk                    (4)

I_avg = ½ × F_clk × C_in × V_in                                (5)

When using pre-charge buffers, the charge provided by the external input amplifier is a fraction of the total charge on the input capacitor. In Equations 6, 7 and 8, G represents the gain of the pre-charge buffer, with an ideal value G = 1 and a typical range of 0.995 < G < 1.005. If you represent the voltage to which the input capacitor charges at the end of the AIN-coarse phase as V_in-coarse, then the charge provided by the pre-charge buffer is:

Q_coarse = V_in-coarse × C_in                                    (6)

V_in-coarse = G × V_in                             (7)

Substituting Equation 7 into Equation 6 results in Equation 8:

Q_coarse = G × V_in × C_in                                      (8)

Since the total charge on the input capacitor at the end of the acquisition phase is C_in × V_in, it becomes possible to represent the charge provided directly by the input terminals as Q_fine, as shown in Equations 9 and 10:

Q_total = C_in × V_in                                (9)

Q_total = Q_coarse + Q_fine                                       (10)

Rearranging Equation 10 results in Equation 11:

Q_fine = Q_total – Q_coarse                                        (11)

Substituting Equations 8 and 9 into Equation 11 results in Equations 12 and 13:

Q_fine = V_in × C_in – G × V_in × C_in                                        (12)

Q_fine = (1-G) × C_in × V_in                                 (13)

Substituting Equations 13 and 4 into Equation 2 results in Equation 14, the average input current when using the pre-charge input buffers.

I_{avg-precharge} = ½ × F_clk × (1-G) × C_in × V_in                                    (14)

Substituting Equation 5 into Equation 14 results in Equation 15. We can now see that the average input current without the pre-charge buffers, I_avg, has now been reduced by a factor of (1-G), where G has a typical range from 0.995 < G < 1.005 for the ADS127L11 delta-sigma ADC:

I_{avg-precharge} = (1-G) × I_avg                  (15)

The external filter capacitor, C_filt, delivers much of the peak current, but there is still a significant amount of dynamic current that the external input amplifier must drive. Much like the reduction in average current, the peak current also drops significantly. Such a reduction in peak current typically reduces the total distortion, which is why using a pre-charge buffer with a high-speed input amplifier can provide better system performance.

The peak input current is limited by the internal AIN-Fine switch resistance, Rsw, and can be calculated using Equation 16. In the case of the ADS127L11, the differential input switch resistance looking into the AINP and AINN terminals is typically 165 Ω. With an input voltage of 4 V and no pre-charge buffer, the resulting peak current, I_peak, during each cycle is close to 24 mA (Equation 17), which is quite high for most precision amplifiers. That is why it’s necessary to use an input filter to deliver the majority of this peak current.

I_peak = V_in/R_sw            (16)

I_peak = 4V/165ῼ = 24mA                        (17)

When using pre-charge buffers, the input sampling capacitor voltage is very close in value to the input voltage when the AIN-Fine switch closes—within the gain error of the pre-charge buffer. In the case of G = 0.995, the pre-charge buffers will charge the input capacitor voltage to about 3.98 V before direct connection to the ADC inputs. The resulting peak input current is now around 121 μA, and can be found by using these values in Equation 18. The results are shown in Equations 19 and 20.

I_peak = (V_in-V_cin)/R_sw               (18)

I_peak = (4V-3.98V)/165ῼ               (19)

I_peak = 121μA                     (20)

As a result of the reduction in both average and peak input current, the pre-charge buffers enable the use of external input amplifiers with bandwidths less than 10 MHz. This opens up many more amplifier choices, making it possible to optimize low-frequency noise, broadband noise, offset voltage and other specifications for the application.

Pre-charge buffer for reference input

The ADS127L11 delta-sigma ADC has also an integrated pre-charge buffer for the reference input. Much like input pre-charge buffers, a reference input pre-charge buffer reduces both the peak and average input current. For the ADS127L11, using a typical external reference voltage of 4.096 V, the average input current without the pre-charge buffer is 778 μA when operating in high-speed mode with a 25.6-MHz input clock frequency. Most references can easily drive 778 μA of average current, but many systems use multiple ADC channels, with eight or more channels.

In the case of an eight-channel system, the total reference current will then be 8 × 778 μA, or 6.2 mA total, which is rather high for a precision reference. As an example, the REF6041 is specified for 4-mA maximum output current, so in this case, a single reference cannot drive eight ADC reference inputs. The REF7025 is another good option, offering excellent low-frequency noise and very low long-term drift. Although the REF70 family is specified for 10-mA maximum output current, in order to achieve the highest accuracy using this reference, the output current should be kept as low as possible.

Using the internal reference pre-charge buffer solves this limitation since the average input current drops to 2 μA per ADC. A single reference can drive multiple channels without any concern of overloading, eliminating the need for additional external amplifiers and reducing overall board size and cost. Figure 4 shows a typical connection using a single reference to drive multiple ADCs with integrated reference pre-charge buffers.

Figure 4 A typical reference connection to multiple ADCs that uses an internal pre-charge buffer. Source: Texas Instruments

Depending on the reference and input amplifier used in the design, you may not need internal pre-charge buffers to achieve your chosen overall system specifications. However, having the option to enable internal pre-charge buffers offers much more flexibility in the choice of external components, providing one more tool to optimize your system design.

More details on the operation and features of precision ADCs—including delta-sigma ADCs and successive approximation register (SAR) ADCs—are available on the TI Precision Labs ADC training series.

This article was originally published on Planet Analog.

Keith Nicholas, applications engineer for precision ADCs at Texas Instruments, is author of Signal Chain Basics blog # 170 for Planet Analog.

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