This unified, pre- and post-silicon verification strategy for 5G designs is based on hardware emulation.
Part 1 of this series discussed how 5G will put an end to the congestion and latency issues.
Designing 5G systems is a daunting task because the technology required to support their powerful capabilities makes them much more complex than their predecessors. This is further aggravated by the need for backwards compatibility/interoperability with equipment based on earlier 4G, 3G, and 2G standards. And, unlike older standards, 5G specifications must support a variety of algorithms and service models used by smartphones, self-driving cars, and IoT devices. Adding to the complexity is that many of these devices have varying degrees of their functionality implemented in cloud-based applications and AI/ML algorithms.
Complexity is not the only challenge posed by 5G systems. System flexibility adds another dimension to the design challenges. The 5G standard is still evolving with new releases issued periodically and no end in sight. This is forcing the companies developing radio-heads, baseband stations, and other 5G core technologies, to only focus on the elements of of the standard that apply to the functionality required for their product, and ignore more global issues that may become a problem later.
5G cellular changes
The unprecedented levels of traffic flowing through 5G networks are generated by a multitude of sources beyond smartphones. These networks provide an on-ramp to the IoT for smart home/building/city devices, smart grid elements, industrial automation systems, autonomous driving vehicles, and an exponentially-growing list of AI/ML applications. The traffic volume, as well as the sheer number and diversity of devices, is forcing the transformation of the radio access network (RAN).
4G RANs had only one job – to connect smartphones to the carrier’s core network. They consist of a series of interconnected base stations, each consisting of a baseband unit (BU) and a remote radio head (RH), and one or more antennas (Figure 1).
Figure 1 4G RAN interconnected smartphones through baseband units and remote radio heads. Source: Mentor, a Siemens Business
Designs for the integrated BU with the RH were conceived and tightly-controlled by the three vendors that dominated the field. This quasi-monopoly led to a closed standard that restricted wider competition. In retrospect, 4G standards CPRI and OBSAI were given quite a lot of freedom that the big vendors used by bringing their own proprietary “flavors” of key technologies (e.g., compression methods) to their solutions. This ensured that the whole end-to-end solution would be provided by one vendor.
5G changes all of the above. The open process used to develop the 5G standard gives cellular operators much more of a say about the functionality and features that go into the equipment they use to build their networks. It gives them the chance to participate in the development of the next generations of highly-configurable networks that can be easily customized to accommodate the needs of regions and cities throughout the world. The truly open global standard also encourages innovation by allowing any hardware/software designer or manufacturer to play a role in 5G product development.
5G also represents a fundamental change in the architecture of the RAN. In 5G, the RAN has morphed into a centralized RAN or C-RAN. The tightly-integrated structure of the 4G RAN has been disaggregated into a “fronthaul network” (Figure 2) that consists of four components:
Figure 2 5G C-RAN enables cell operators to control and drive open standards. Source: Mentor, a Siemens Business
The disaggregation of the C-RAN allows for installing CUs, DUs, and RUs remotely from each other, leading to several advantages:
Other benefits of the C-RAN network include the ability to flexibly pool resources, reuse infrastructure, simplify network operations and management, and support multiple technologies. From an OPEX perspective, they offer lower energy consumption, and lower capital and operational expenses.
Because the 5G network structure is more heterogeneous and self-organizing, it’s easier for them to evolve to meet changing market conditions and new opportunities. And, since the C-RAN is easier and faster to deploy, it avoids having to rebuild the transport network, another factor that dramatically reduces its total cost of ownership (TCO).
A 5G network can be customized as needed in cities and rural areas, leading to many hardware/software configurations and use cases available to cellular operators. Such flexibility stems from the open radio access network (O-RAN) standard, an open standard defined by the O-RAN Alliance, a large alliance of telecommunication industry members. It defines open, interoperable interfaces, APIs, RAN virtualization, and big data-enabled RAN intelligence. The goal of the standard is to utilize the same physical cables used within an Ethernet network. The O-RAN Alliance is also involved with the other Ethernet-based protocols used in 5G networks, including enhanced common public radio interface (eCPRI) and radio over Ethernet IEEE1914.3 (RoE).
5G fronthaul design verification
The increased 5G complexity, driven by many applications and use cases, is exacerbated by a plethora of equipment configurations, creating a situation which requires much more extensive testing than 4G does. This includes larger functional verification suites that embrace most modern verification techniques, such as formal verification assertions and coverage, fault, design for test (DFT), design for manufacturing (DFM), etc. Expanded analyses must be used for performance and power consumption, interoperability, protocol compliance, stress tests, analytics, and more.
The semiconductors used in 5G products frequently implement complex, leading-edge technologies. To prevent discovery of incompatibilities, functional errors, or security flaws when it’s too late (and too expensive) to fix them, each device will require thorough pre-silicon verification before releasing the design database to manufacturing, as well as post-process testing on the first silicon returning from the foundry.
Today, the pre-silicon verification engineer can pick and choose from a spectrum of verification engines and methodologies, ranging from traditional register transfer level (RTL) simulation, to hardware-based verification using prototypes built from one or more field programmable gate arrays (FPGAs).
RTL simulation running on accurate software models of intellectual property (IP) blocks offers versatility, interactivity, and powerful debugging capabilities. These advantages have made it a necessary tool for early testing of IP blocks. However, the immense size and complexity of RTL files cannot be run at anywhere close to “real time” speeds on most computers, making it difficult, or impossible to perform system level validation, and validation of embedded software.
Alternatively, hardware prototyping with FPGAs offers testing at three or four orders of magnitude faster than RTL simulation, but it still runs at one or two orders of magnitude slower than real silicon. The slower speed limits the scope of most validation campaigns to selected time windows within an execution run that may involve trillions of clock cycles when booting an OS and running compute-intensive applications. In addition, FPGA-based validation does not have the flexibility and debugging capabilities of the RTL simulator.
In between the RTL simulator and FPGA prototyping sits hardware emulation. A modern hardware emulator can selectively take on many tasks that are customarily implemented in software by the RTL simulator. Unlike a pure software strategy, it can carry out those tasks on designs of virtually unlimited sizes, at orders of magnitude faster than simulation. Stated simply, hardware emulation is mandatory in any verification flow.
Post-silicon testing is typically performed in a lab via either an in-house built tester or ad-hoc automatic test equipment. In this example, we’ll use Mentor’s X-STEP system to illustrate how hardware emulation tools are being used for verification and testing of silicon for 5G devices. X-STEP, developed by Mentor, a Siemens Business, comes with a large library of pre-verified test suites, derived from the 5G protocols that are fully-compliant with the standards. This eliminates the time, expense, and potential risks involved with creating the stimulus for the software simulation in-house. It also eliminates the need for developing your own prototyping environment.
Figure 3 shows the X-STEP tester environment, including setup files, stimulus files, and the objects necessary to run the tester. The system includes tools and software to create the setup files and analyze DUT results using advanced analytics.
Figure 3 X-STEP, configured for silicon-level testing of 5G devices, comes with a built-in suite of standards-compliant 5G protocols. Source: Mentor, a Siemens Business
Unified pre- and post-silicon verification
Historically, pre- and post-silicon testing occur in two separate verification stations that do not share data, methods, or personnel. This process is inherently inefficient and time-consuming, and can impact critical time-to-market timelines.
A proposal for a unified pre/post-silicon verification strategy improves the efficiency, as well as the early interoperability validation of 5G design/products. The approach calls for creating a pre-silicon environment that mimics the post-silicon setup and is capable of sharing and exchanging the test parameters and other critical data between the two setups. The technology that makes this possible is the virtualization of the test environment that drives an emulator. The model, part of the Veloce VirtualLAB library, can run in a state-of-the art emulation platform or a leading-edge prototyping system. The only difference is the speed of execution that decreases when moving from the hardware test environment to the prototyping to emulation.
Since the setup is accurate and configuration tasks are reduced to a minimum, the verification team can switch between pre- and post-silicon at will, testing all performance cases in pre-silicon for bandwidth, latency, etc. Figure 4 captures the essence of the unified strategy, and highlights the common setup shared with post-silicon testing performed via X-STEP, as shown in Figure 3.
Figure 4 A unified pre/post-silicon verification strategy improves efficiency, as well as early interoperability validation of 5G designs. Source: Mentor, a Siemens Business
To summarize, Figure 5 portrays the full range of verification options made possible by the unified verification strategy, and a comprehensive set of verification tools that can plug in anywhere during the development cycle of a 5G embedded product.
Figure 5 A unified verification strategy with a set of verification tools can plug in anywhere during the development cycle of a 5G embedded product. Source: Mentor, a Siemens Business
The pre/post-silicon unified testing environment enables thorough verification of hardware and validation of embedded software, including system validation during every phase of the development cycle. Essentially, it allows any test to be ported anywhere up and down the verification spectrum in the development cycle, creating a comprehensive validation library that can be interchanged from product to product for internal projects in a single company or between two vendors testing product interoperability.
As an example, let’s assume that Company A develops a 5G chip that will be used by Company B in its DU. With unified verification, Company B is able to test its DU during system integration using exactly the same tests that Company A ran to verify the functionality of its chip.
Verifying the SoCs used in 5G equipment is a daunting task because the standard they support is extremely complex, conceived to support many applications and use cases. This poses a critical challenge to verification teams that must meet time-to-market demands with quality products.
The traditional pre/post-silicon test strategy requiring two separate teams using two independent methodologies is no longer acceptable. One of the most promising approaches is to merge the pre- and post-silicon test methodologies into a unified verification strategy. The virtualization of the post-silicon physical test environment, when executed on a modern emulator, establishes a bi-directional flow that allows designers to run the same tests on the emulator and on the X-STEP tester. With X-STEP, partners can exchange fronthaul test configurations in an executable format to enable ecosystem-wide cooperation, thorough verification, and interoperability between devices from different vendors.
Dr. Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.
Mika Castren is a senior engineering and product development manager with Mentor, a Siemens Business.
Ron Squiers is a solution networking specialist at Mentor, a Siemens Business.