Using AI to pattern sub-10nm ICs

Article By : Steffen Schulze

Meet the challenges of patterning sub-10nm ICs with a closed loop design and manufacturing optimization methodology, combined with machine learning.

As semiconductor technology advanced from 65nm to 7nm over the last 10 years, new challenges have arisen in design and manufacturing. Securing the IC yield means developing new methods that respond to findings during the manufacturing ramp, and update design flows in fast and efficient ways. New tools (the most sophisticated of which employ machine learning algorithms) and an enhanced methodology called closed loop design and manufacturing (D&M) optimization help to facilitate that.

Starting at the 22nm process, the lack in reduction of the exposure wavelength forced foundries to turn to multi-patterning – the use of multiple photolithographic exposures to print features with sufficient resolution onto devices. As ICs got even smaller, the complexity of interactions between the growing number of features and layers that silicon foundries can manufacture onto an IC have been growing exponentially.

In response to the vastly increasing number of design rules, vendors of EDA (electronic design automation) equipment had to develop new tools to account for critical dimensions in features and new overlay specifications required for manufacturing equipment to implement multi-patterning effectively.

Despite this effort, it is getting increasingly difficult to anticipate and capture all manufacturing constraints properly with design rules.

Let’s look at the challenges of critical layout patterns in individual and multilayer layer processing. Then we will look at the tools to characterize and manage these patterns from design to manufacturing, manufacturing to test, and back to design in a learning loop – closed loop D&M optimization. We’ll also look at how these new tools in the closed loop D&M optimization flow apply machine learning methods to reduce the number of iterations and the time it takes for each learning cycle.

Non-linear growth in pattern complexity
The number of layers that can be implemented on a silicon device and the number of features that can be implemented on each layer of an IC or a silicon wafer (and the density of the features on each layer) have essentially made it impossible for manufacturing equipment to use traditional single pattern lithography to accurately print features onto silicon with an acceptable yield of working devices.

Extreme ultraviolet (EUV) lithography technology – which is now finally being deployed – is showing promise in helping to alleviate some of the design and manufacturing complexity. Perhaps ironically, the deployment of EUV has been limited, due mainly to the complexity of EUV equipment, compounded by its technological immaturity and cost. Most foundries, even those that also use EUV on some layers, employ multi-patterning as a way to accurately print features in greater density onto the growing number of layers of the silicon.

Figure 1 illustrates the field of complexity to print, and also how testing the device has grown non-linearly as the industry advanced to 10nm and then on to 7nm.
Figure 1 The complexity of interactions and number of geometries interacting is growing nonlinear.

In general, there are many drivers for complexity – including material, equipment, and the general need for tighter specifications that insert a higher order of interaction into the field of interest. Although, from a patterning perspective, two trends stand out: the interaction of layers and the number of features (or feature density) in the optical radius, which is the zone of influence that is typically considered during optical proximity correction (OPC) and the application of resolution enhancement techniques (RET). The optical radius is roughly 3 times larger (~0.6um) than a scanner’s wavelength (193nm), which has stayed constant for a number of process generations.

Since the unit area of a device is shrinking, we see a growing number of patterns that can influence the printing behavior of a particular feature of interest (see center of Figure 1). In addition to an increase in density, the layer-to-layer interactions are also increasing. With the use of multi-patterning the correct placement of shapes next to each other, and also their placement relative to the shapes in adjacent layers (above and below) becomes critical. In order to account for these tighter critical dimensions, overlay specifications must be reflected accurately in physical design tools to ensure design compliance as well as chip yield.

Indeed, EDA vendors are constantly updating their tool offerings to account for these new, more complex rules. Figure 2 illustrates this dramatic increase over several generations of silicon process technologies.

Figure 2 The advanced physical verification effort is growing to capture increased interactions.

The 65nm to 32nm transition saw a trifold increase in the number of rules. The 32nm to 16nm transition saw a 1.6× increase. And we are seeing that the 16nm to 7nm transition sees an increase of about 3.6x. We can also see that the trend is accelerating towards more rules over the most recent generations despite efforts to simplify technology and use more restricted design rules. As a side note, this is also a reflection of the difficulty to meet the power-performance-area (PPA) benefits of moving to a new node, as electrical effects also play into this equation (though not addressed in detail for this article).

Progression of physical verification and design for manufacturing

In addition to updating tools to accommodate more design rules, the EDA and semiconductor manufacturing industries are constantly developing new technologies to enable “zero error” pass downs from design to manufacturing.

To this end, the two industries have developed new features and functions to improve manufacturing yield. These include context sensitive checks such as equation-based DRC supporting multi patterning techniques, the introduction of FinFET technology, and the advent of specific processing requirements, such as density balancing between layers to retain single etch processes in the processing of a multi-patterning stack.

Optical Proximity Correction has also evolved. EDA companies expanded OPC to comprehensively capture more failure sources – from the simple verification of the convergence of the OPC solution to finding true intra-layer and inter-layer failures. Today, we can comprehensively assess layer interactions and process windows, and we are leveraging stochastics to improve these assessments.

Along with the new technologies, new methodologies have also emerged such as the dummy fill insertion methodology, which enables companies to tune fill better to a specific patterning environment.

[Continue reading on EDN US: Technology progressions]

Steffen Schulze is the director of product management for Calibre Semiconductor Manufacturing Solutions.

Related articles:

Leave a comment