As the space industry continues to exploit high data rates, the channel loss between the transmitter and the receiver becomes more and more important.
Satellite manufacturer are taking advantage of high-speed serial links to connect multiple FPGAs/ASICs on a single PCB and/or transfer data between modules. As bit rates increase, spacecraft OEMs are grappling with how to measure and characterise the performance and reliability of SERDES channels to ensure sub-systems are developed right-first time.
Previously we discussed the use of IBIS-AMI simulation to predict the performance and signal integrity of high-speed serial links before manufacturing your PCB. In this post, I want to share some experiences of using a bit-error rate tester (BERT) to measure and validate the hardware operation of SERDES links. You have spent many months designing your latest avionics, the PCB has been fabricated and assembled, the initial, power-up commissioning and basic functional tests have been successful, and you are now an eager beaver to measure the full performance and capability using the high-speed links.
For those of you not familiar with hardware testing of SERDES channels, a BERT sends a known data stream such as a PRBS down a link comparing the received waveform with the original. Any differences are noted and using this information, a bit error rate (BER) can be calculated for full, end-to-end performance, including the transmitter, the physical medium, and receiver.
As the space industry continues to exploit higher data rates, e.g. 5, 10 Gbps and above, the channel loss between the transmitter and the receiver, e.g. PCB traces, connectors, and cables, becomes more and more important because of high-frequency effects such as greater dielectric absorption, skin effect, and conductor losses. These result in intersymbol interference (ISI), i.e. distortion of the current bit due to the logic state of previous bits, increasing jitter, resulting in more data errors thus limiting the maximum data rate.
The latest BERTs enable accurate characterisation of multi-lane receivers and emulate channel loss by injecting various, controlled-jitter sources, common and differential-mode interference, transmitter pre/de-emphasis and receiver clock recovery/equalisation options. Sequences of data patterns such as PRBS, pulse, clock, static, and memory encoded using a variety of symbols, e.g. 8B/10B, 128B/130B, and 128B/132B, can be created to simulate the bit streams your avionics will receive during operation. In my case, I use Keysight's M8020A J-BERT to measure the performance of hardware SERDES links.
__Figure 1:__ *The Keysight M8020A, 4-channel, 16 Gbps J-BERT.*