Vias are really cool

Article By : Douglas Brooks & Johannes Adam

The temperature of a via is not determined by the current flowing through it, but by the temperature of the parent trace.

Up until recently, most of us assumed that we treat the thermal characteristics of vias the same way we treat the thermal characteristics of traces. And we would use the IPC 2152 thermal guidelines for sizing vias. Indeed, the IPC formalizes this idea on page 26 of the publication titled “Standard for Determining Current Carrying Capacity in Printed Board Design” as follows:

The cross-sectional area of a via should have at least the same cross-sectional area as the conductor or be larger than the conductor coming into it. If the via has less cross-sectional area than the conductor, then multiple vias can be used to maintain the same cross-sectional area as the conductor.

In a recent article, we explored the thermal characteristics of traces using Thermal Risk Management (TRM), an electro-thermal simulation tool. We have shown that TRM effectively simulates the IPC data and how to estimate the degree to which other factors such as material parameters and layout considerations could further impact trace temperatures.

It occurred to us that if TRM could analyze trace temperatures, it might also be able to analyze via temperatures, especially the temperatures at the mid-point of the via. No one had been able to do that before. When we began exploring that possibility, what we found was really cool, literally.

Modeling vias

For this article, we developed a basic board and trace model as shown in Figure 1. The board is 120-mm long by 20-mm wide. There is a trace that is 52-mm long on the top layer and a corresponding trace on the bottom layer extending toward the far end of the board. These traces are 0.034-mm thick (approximately 1.0 oz). The traces are connected by a 0.26-mm diameter via plated to a thickness of 0.03 mm. That approximates a 10-mil diameter via plated to a 1.0-oz thickness. The board material is modeled as standard FR4, 1.6-mm (approximately 63-mils) thick. Various trace widths and currents are modeled.

Figure 1 This diagram of the via placement was derived from an actual simulation.

We also employed a second model, identical to this one, except that there is a 100-mm long trace on the top layer with no via and no trace on the bottom layer. This model was used to measure the trace temperature for the same current as used in a via model, but for the case of no via.

Model results

Our first model is for a 0.64-mm (approximately 25-mil) wide trace carrying 3.5 A. We selected this width because it has an almost identical cross-sectional conducting area as the via. Figure 2 is the simulated thermal image for this trace.

Figure 2 This thermal image shows the modeled 0.64-mm wide trace with 3.5 A.

There is a very important result that is barely perceptible in Figure 2. Figure 3 expands the via region of Figure 2 with a narrowed thermal range. The via is cooler than the trace. The maximum temperature of the via is 67.7°C, while the temperature of the trace behind the via is 69.5°C, almost 2 degrees hotter. The via is helping to cool the trace.

Figure 3 This expanded thermal region shows that the via is helping to cool the trace.

If we decrease the trace width, while keeping the via dimensions same, the situation becomes even more pronounced. Figure 4 shows a close-up of a smaller 0.5 mm, approximately 20 mil-wide simulated trace carrying 3 A. In this case, the via is 3.4°C cooler than the trace.

Figure 4 This simulated 0.5-mm trace is carrying 3 A into the same 0.26-mm via.

These results reveal a universal truth. If the via conducting surface area is the same or greater than the conducting surface area of the parent trace, the via will always be cooler than the trace.

When you stop to think about it, the results make intuitive sense. One of the surprises reported in IPC-2152 is that internal traces are cooler than external traces of the same dimensions carrying the same current. Prior to IPC-2152, most designers had assumed internal traces were hotter because they were insulated from the air by the dielectric. But it turns out the dielectric is a better conductor of heat than is convection (and radiation). Vias, being surrounded by dielectric, are cooled more efficiently than traces, which have dielectric only on one side. Therefore, they are cooler than the external traces on the surface.

If the external traces have significantly more conducting surface area than a connecting via, the situation changes. But not by as much as you might think. Table 1 provides the results of selected simulations. When the trace area gets significantly larger than the via area, the via temperature rises above the trace temperature.

Table 1 The via temperature rises above the trace temperature when the trace area gets significantly larger than the via area.

A 2.5-mm wide trace, for example, has four times the conducting cross-sectional area as our hypothesized via. At a current of 6.5 A, the via temperature is about 8°C above the trace temperature. That is higher, but maybe not dangerously higher, than the trace. But consider this: a current of 6.5 A through a trace whose cross-sectional area is 0.218 mm² (the same as our via) would raise the trace temperature well over 350°C and possibly melt the trace. Our via is nowhere near that kind of level.

Again, when you stop to think about it, the results make intuitive sense. A via might be 40 to 120 mils long. The two traces it is connected to are dramatically larger. So, the traces act as heat sinks for the via. The heat is conducted quickly away from the via by the larger thermal mass of the traces and then conducted back into the dielectric. Vias simply can’t get a lot hotter than the parent trace, unless we design something really extreme.

Bottom line

The temperature of a via is not determined by the current through it. It is determined by the temperature of the parent trace. Even small vias can be used in thermal situations. For equivalent cross-sectional areas, vias are cooler than traces. When traces are larger than vias, “excess” heating in a via is conducted away by the heat-sinking actions of the parent trace and the via will be protected.

Editor’s Note: Authors Brooks and Adam, in their recent book PCB Design Guide to Via and Trace Currents and Temperatures, show several examples of simulated vs. actual controlled experimental results. The clinchers are when they pass relatively large currents through small vias without any harm. These are currents that would otherwise damage normal traces with the same cross-sectional area.

Douglas Brooks has written two books and numerous technical articles on PCB design. He gives seminars on PCB designs around the world.

Johannes Adam has worked on numerical simulations of electronics cooling at companies like Cisi Ingenierie, Flomerics and Mentor Graphics. He currently works as a technical consultant.

This article was originally published on EDN.

Other articles in this series:

• Major design considerations for determining PCB trace temperature

Related articles:

• Designing controlled-impedance vias
• Via spacing on high-performance PCBs
• No place to hide from PCB thermal and RF considerations
• Talking a closer look at PCB traces
• High-Power PCB Design
• PCB signal coupling can be a problem

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