Calibre DESIGNrev tool is a fast and flexible chip-finishing platform that helps speed up design completion and tape-outs by rapidly loading, displaying, and editing large GDSII and OASIS layouts whereas the Calibre Foreign Database Interface (FDI) utilities enable LEF, DEF, and OpenAccess read/write as well as Oasis to DEF back annotation & LEFDEF DRC Checking. During this forum, we would also demonstrate various Calibre XOR flows along with FastXOR which provides fast Layout versus Layout application to validate differences between large block and chip level design iterations.
Attend this Free technical webinar to explore Calibre DesignREV platform for faster chip integration & LEF/DEF Interface for P&R flows.
What You Will Learn:
-Handling Large Layouts Quickly and Efficiently Automates Chip-finishing Task
-Flexible Chip Review with Overlays, Multi-window synchronization
-Supporting of the open standard TCL/TK macro language for extensive tool customization
-Tight Chip integration with DESIGNrev FileMerge flow
-Layout Comparison flows with Calibre DBDiff, XOR & FastXOR utilities
-Calibre FastXOR performance optimization
-FDI LEFDEF utilities & applications like Back annotation, LEFDEF DRC checking etc
Corporate Application Engineer
Siddhanta Sahu working as a Corporate Application Engineer in Siemens EDA supporting on Calibre products. Siddhanta has 5+ years of experience into VLSI Designing & EDA support role. Siddhanta has worked as a SOC Designer & sign-off engineer in various ASIC projects prior to joining Siemens EDA. Siddhanta did his Bachelors in Electrical & Electronics Engineering from Veer Surendra Sai University of Technology, Odisha.
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