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A “worst case” analysis of rail voltage decoupling for a digital circuit board was required, but the challenge was to determine what the worst case current pulse circumstances could actually be.

The task at hand was to show that the rail voltage being delivered to a rather densely-populated circuit board would not experience more than 40 mV of transient excursions in response to each ampere of circuit board current steps. The rise and fall times of those steps (from 10% to 90% and from 90% to 10%) were defined as being no faster than 3 nsec.

The first part of this analysis was to characterize the current excursions. Two models were devised: one model was a sine tip and the other was an offset cosine. In both cases, the parameters of the pulse contour were derived to yield 3 nsec rise time and 3 nsec fall time, as in **Figures 1 and 2**.

The key difference between these two pulse models is that the sine tip has corners at the current flow starts and stops and where the first derivative changes abruptly. The offset cosine model makes those transitions smoothly and has no first derivative abruptness. The effects of that will be evident shortly.

**Figure 1** The sine tip pulse model has corners at the current flow starts and stops and where the first derivative changes abruptly.

**Figure 2** The offset cosine pulse model makes transitions smoothly and has no first derivative abruptness.

Overlaying the two pulse models, it can be seen that despite their difference, they do approximate each other pretty well.

**Figure 3** The pulse models approximate each other pretty well.

**Figure 4** Circuit board and power supply capacitors could be taken as five R-L-C combinations.

It was ascertained that the capacitances on the +5V rail could be taken as five R-L-C combinations, some of which applied to single capacitors and some applied to groups of capacitors. The performance analysis method was to inject current pulses in compliance with the chosen pulse model and to use recursive differential equations to examine the resultant voltage shown in **Figure 5** as “e.”

**Figure 5** Recursive differential equations were used to examine the resultant voltage (j = 5 for our example).

Since the load current was being drawn from the capacitor assembly instead of being pumped to that assembly, the calculated voltage “e” is what had to be subtracted from the +5V rail.

The results were plotted as follows:

**Figure 6** These plots show the rail voltage excursions for both pulse models.

These results showed that both current pulse models complied with the <40 mV requirement. We should note that the step changes in rail voltage for the sine tip model arise from the abrupt di/dt of the sine tip, which in the real world would only be an approximation to actual events.

*This article was originally published on EDN.*

*John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE). *

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