What CXL 3.0 specification means for data centers
Article By : Majeed Ahmad
The CXL 3.0 specification provides a range of advanced features and benefits, including doubling bandwidth with the same latency.
The CXL Consortium has announced the release of the CXL 3.0 specification to add new levels of flexibility and composability in the present and future data centers. CXL 3.0, built on the previous technology, provides a range of advanced features and benefits, including doubling bandwidth with the same latency. It’s backward compatible with CXL 2.0, CXL 1.1, and CXL 1.0 specifications.
Computer Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices like accelerators, memory buffers, and I/O interfaces. Its newest version, CXL 3.0, adds advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains.
Siamak Tavallaei, president of CXL Consortium, said that CXL technology is quickly evolving to meet data center requirements. “Modern data centers require heterogeneous and composable architectures to support compute-intensive workloads for applications such as artificial intelligence and machine learning,” he added. “The CXL 3.0 specification will enable new usage models in composable disaggregated infrastructure.”
Kevin Krewell, principal analyst at TIRIAS Research, acknowledges that the CXL Consortium has made exceptionally swift progress in delivering this critical specification to the industry. “CXL 3.0 is a significant step forward in enabling heterogeneous computing.”
Travis Karr, general manager of interconnect SoCs at Rambus, agrees on the transformative potential of the CSL technology and its latest version. “The introduction of CXL 3.0 meets the needs of next-generation data centers with 64 GT/s signaling and a new level of scalability.”
The CXL Consortium will introduce the new CXL 3.0 features at the Flash Memory Summit (FMS) being held on 2-4 August at the Santa Clara Convention Center.
This article was originally published on EDN.
Majeed Ahmad, Editor-in-Chief of EDN and Planet Analog, has covered the electronics design industry for more than two decades.