Capacitive loads can make chopper-stabilized op amps unstable.
In olden days, when op amps used ±15 V supplies and input/output signals were ±10 V, we had few problems with input/output limitations. Our op amps output impedance (Zo), small-signal AC impedance, open-loop output impedance was resistive: 25 Ω to 50 Ω. Even 1 nF capacitive loads on the output had no adverse effects. Those days are gone.
Today’s op amps, however, use many different architectures for rail-to-rail input and rail-to-rail output as well as very low offset and offset drift. Zero-drift and/or chopper-stabilized op amps achieve this low offset and drift. Modern zero-drift or chopper-stabilized op amps have complex Zo, small-signal AC, open-loop output impedance. From low frequency to high frequency, the Zo can be resistive, inductive, “double-inductive,” inductive, and then finally resistive. Because of their complex Zo, zero-drift or chopper-stabilized op amps can become difficult to stabilize with capacitive loads unless you use a methodical approach to design. (Key fundamental tools for op amp stability are assumed to be known and the “recommended reading” at the end of this article gives direct links where these fundamentals may be obtained.)
Zero-drift and chopper-stabilized amplifiers can have complex output impedances that make it difficult to stabilize when capacitive loads appear on their outputs. I’ll show how to use Riso with dual feedback to compensate for capacitive loads for a chopper-stabilized op amp. This definition should, by example, enable you to use other stability compensation techniques to stabilize chopper-stabilized amplifiers by accounting for the interaction of Zo and load impedance (ZL). One key concept that is critical to understand in this analysis is the op amp’s complex Zo and its interaction with the capacitive load. Once compensated for the op amp, an application circuit becomes stable.
The op amp AC model shown in Figure 1 is all we need to analyze op amp stability issues. The difference between –IN and +IN is gained up by x1 through VCVS1, a voltage-controlled-voltage source, that has infinite input impedance and zero ohms output impedance. The output of VCVS1 is fed into a block that is the datasheet open-loop gain (Aol) transfer function. The Datasheet Aol block feeds into a Zo (small signal, AC, open loop output impedance) block. The ZL block represents whatever load is connected to the output of the op amp at Voa. Connecting any external ZL to the op amp output will change the datasheet Aol and result in a new application specific Aol we call “loaded Aol”.
The OPA388 is a precision (ultra-low offset voltage=±0.25 µV and zero drift=±0.005 µV/°C) chopper-stabilized op amp. Characteristic of these op amps is a complex Zo (small signal AC, open-loop, output impedance), as shown in Figure 2. Starting at low frequency and going towards high frequency we see the Zo is resistive (0 dB/dec), then inductive (+20 dB/dec), then “double-inductive” (+40 dB/dec), then inductive (+20 dB/dec), and then finally resistive (0 dB/dec). This complex Zo can make compensating capacitive loads tricky without a systematic approach.
Our capacitive load will be selected to be a 1 µF capacitor. The impedance curve for a 1 µF capacitor versus frequency is shown in Figure 3.
The OPA388 op amp macromodel will be used to simulate and plot the OPA388 Zo characteristic using the test circuit shown in Figure 4
Figure 5 shows the resultant Zo simulation for the OPA388, which matches that of the datasheet Zo curve.
When we combine the ZL (1 µF capacitor impedance) and OPA388 Zo curves on the same graph in Figure 6 we immediately see a stability concern. First order slopes are shown for Zo. At fx we see that the rate-of-closure, difference in slopes between ZL and Zo are either 40dB/dec or 60dB/dec. Either of these slopes implies a resonance condition due to the interaction of ZL and Zo.
Our test circuit for measuring the loaded Aol of the OPA388 with a 1 µF capacitive load is shown in Figure 7.
The loaded Aol curve of the OPA388, with a 1 µF capacitive load, is shown in Figure 8. Note the region between 10 kHz and 20 kHz, which shows a very abrupt phase shift in the phase plot and a hump, or peaking, in the magnitude plot. These characteristics indicate a resonance in the Aol curve and no additional compensation tricks can make this circuit stable.
We will conduct a transient load stability test using the circuit of Figure 9 to see if our OPA388 with 1 µF capacitive load is stable in the time domain. IG1 is a current generator set to 1 kHz, 1 mApk, and 1 ns rise/fall time. This will create step disturbances in the system so we can see the natural response of the closed loop system to look for any excessive overshoot and ringing, which will indicate marginal or complete instability.
Our transient stability test results in Figure 10 and Figure 11 (zoom-in) clearly show that we have an unstable circuit. If we zoom in on the results of the transient stability test, we see sustained oscillations after an initial step change of load current. This indicates an unstable circuit.
If we plot OPA388 Zo and the impedance for a CL=1 µF capacitor, as shown in Figure 12, we can add RL=10 Ω, 30 Ω, 100 Ω impedance lines as shown. Our loaded Aol will see the series combination of impedances for RL and CL. At frequencies above where RL crosses CL, RL will dominate the net ZL impedance since for two impedances in series, highest value wins. To avoid resonance between ZL and Zo we need <20 dB/dec slope difference. To achieve this and minimize the frequency range over which RL will interact with an inductive region of Zo, we choose RL=100 Ω as shown in the net ZL curve.
Our loaded Aol will be the datasheet Aol run through our Zo_ZL_Divider network, as shown in Figure 13. From 100 Hz to 100 kHz, Zo << ZL so we expect little effect on the datasheet Aol curve passing through the Zo_ZL_Divider. From about 100 kHz to 300 kHz we expect the datasheet Aol to be attenuated by addition −20 dB/dec since Zo > ZL and Zo is increasing at +20 dB/dec.
Shown in Figure 14 is a practical implementation of our CL=1 µF, RL=100 Ω. This supply splitter divides the 5V supply in half for a mid-supply reference point commonly used in single supply systems for offsetting and scaling. The OPA388 sees a ZL=R1+CL and Voa is the loaded Aol measurement point. Note that since the internal input capacitances of the OPA388 are isolated by L1 we move them out externally by the addition of Ccm and Cdiff.
A simulation plot of our supply splitter circuit shows the expected loaded Aol (Figure 15).
The test circuit of Figure 16 will be used to obtain loaded Aol, and 1/Beta_FB#1 (Voa through R1 & CL through R2 and back to –IN of OPA388).
Our test circuit in Fig. 16 lets us easily plot the loaded Aol and 1/Beta_FB#1 (Figure 17). At fr, where 1/Beta_FB#1 intersects the Loaded Aol, and where loop gain (AolBeta) goes to 0 dB, the rate-of-closure is 60 dB (|-40 dB/dec −(+20 dB/dec)|). This is unstable.
If, however, we draw in a second feedback path, 1/Beta_FB#2, we can make the circuit stable. With two independent feedback paths the highest Beta or lowest 1/Beta wins and that is the dominant one the op amp will see. The 1/Beta_Net shown above intersects the loaded Aol at fcl with a rate-of-closure equal to 20 dB/decade. From the first order stability check this implies stable operation but will require a loop gain magnitude and phase plot to determine final phase margin. Note that we place fz1, in the 1/Beta_FB#2 path about ½×fw, where the two feedback paths cross. This rule of thumb ensures with component tolerances that we never create “The Big Not” where there would be a peak in the 1/Beta_Net response, which can make the circuit unstable. The Big Not is covered in the stability material reference in the appendix. At fw, about 16 kHz, where 1/Beta_FB#2 becomes dominant the control of 1/Beta_FB#1 is lost and disturbances at Vout cannot be reacted to for frequencies above 16 kHz.
Now we go back to our original circuit to determine where to add in 1/Beta_FB#2. The high frequency gain of 1/Beta_FB#2 is set when CL = short and C4 = short and so can be approximated by R5/R2. Because CL will be >>: C4, CL will be a short before C4 is a short and so fz1 can be determined by C4 and R5, as shown in Figure 18.
As shown in Figure 19, the final loaded Aol and 1/Beta_Net follows our predicted first order approximations created by drawing in a 1/Beta_FB#2 curve on the loaded Aol and 1/Beta_FB#1 plot.
A final loop gain magnitude and phase plot confirms a stable circuit with 64.8 degrees of phase margin at fcl where loop gain = 0 dB, and no rapid phase shifts in the phase plot or peaking in the magnitude plot, as seen in Figure 20.
The load transient stability test results of Figure 22 confirm that out of the op amp, Voa, there is not excessive overshoot or ringing due to a sharp step disturbance at the output.
A final check of the closed loop AC transfer function will reveal what the bandwidth control is at Vout using the test circuit in Figure 23.
Our first order 1/Beta plots showed that around 16kHz 1/Beta_FB#2 began to dominate. Here the final results in Figure 24 show −3 dB closed loop bandwidth to be 25 kHz. You can derive all of the math to predict this but with an accurate op amp SPICE macromodel (with Zo and Aol matching datasheet) why not let the simulator do the work?