Why FPGAs and analog haven’t mixed well so far

Article By : Don Dingee

FPGAs and analog haven't mixed well, but that may be starting to change with new chiplet technology integrating analog blocks.

FPGAs enjoy massive popularity among advanced digital designers, helping bring customized low- and mid-volume designs to market quickly without investments in ASICs. FPGAs also blend performance with flexibility, changing functions via reprogramming. Makers are also moving into the mid-range FPGA realm with easier-to-use tools.

But for analog aficionados, FPGA-like programmability has been elusive. For the most part, FPGAs and analog haven’t mixed well—but that may be starting to change with new chiplet technology. Let’s look briefly at what’s happening.

It’s a transistor-powered world

While I’d hesitate to say digital design is simple, especially at higher speeds, some characteristics make it more manageable than analog design. One of the motivations for A/D conversion is to get signals out of the analog domain and into digital as quickly as possible, improving noise immunity and putting fast digital processors to work.

However, not all transistors are created equal. Transistors used as digital switches can be driven hard, transitioning between ‘zero’ and ‘one’ levels as fast as possible. Using transistors for analog signals requires more care and feeding. There are issues around noise, ground loops, power supply, non-linearity and distortion, current draw, parasitic capacitance and inductance, and more.

Digital designs tend to be drawn to cutting-edge semiconductor processes, with today’s advanced nodes pushing to 3 nm and 2 nm. Tiny geometry allows packing more transistors into a chip, which is handy when dealing with complex digital processor cores—or a large FPGA. Smaller geometries also mean lower operating voltages, saving power, and faster clock speeds.

On the other hand, analog-friendly processes are less aggressive. Mature mixed-signal processes are in the 30-nm range; TSMC has just announced a mmWave RF process at 16 nm. So, mixing analog and digital cells on the same die gets tricky because of the disparity in voltage and current and different design rules. That’s why foundries go to great lengths to characterize process design kits (PDKs), explaining the parameters for the different types of cells they offer.

A sea of analog blocks sounded good at the time

Most FPGAs created for supporting digital logic have four primary features: logic blocks, memory blocks, interconnect, and off-chip digital interfaces. The last feature may require transistors hardened for higher voltage levels or extra current drive, but they are still digital switches.

An analog FPGA sounds like a good idea until one tries to put it into practice. So far, the closest attempt has been the Infineon’s PSoC family, which came from its Cypress acquisition. The PSoC 6 is really a microcontroller with moderate performance A/D, D/A, and other selectable hardened analog blocks available for interfacing. But it’s not a sea of “soft” analog blocks that can be connected any way a designer pleases. Where does the sea-of-blocks idea run into trouble?

  • Interconnect It would be tough to create an analog interconnect that could carry signals of sufficient quality to any point across a large FPGA. Trace lengths and added impedance from switches would change behavior and provide paths vulnerable to noise and ground loops.
  • Layout Hardened analog cells work because layouts are kept tight, with short, balanced paths and appropriate steps in power and grounding. As mentioned, intermingling digital and analog cells starts to disrupt one way or the other.
  • Tools Digital simulation tools are mature and produce excellent results, even dealing with clock domain crossing issues common to FPGAs. Analog simulation tools are only as good as the models therein, and predictions can degrade quickly in the face of parasitics, thermal effects, charge trapping, and more real-world behavior. Circuit simulation must combine with electromagnetic simulation for good results.

Chiplets may change everything in FPGAs

That’s why the Intel Agilex Direct RF-Series FPGAs caught my eye. They’ve integrated 64-GSPS A/Ds into the FPGA using a chiplet approach. Chiplets are just what they sound like—a small design on a small die dropped onto a larger die. A chiplet can use different design rules, even an entirely different process technology, from the base part. Intermingling problems disappear. A/D, PCIe, and optical interfaces are optimized on their own merits in separate chiplets, as is the case in digital FPGAs.

Source: Intel

It’s still not the sea-of-analog-blocks approach some may expect. Still, high-performance chiplets integrate easier than hardened monolithic analog cells, opening the door to things like faster sample rates and higher resolution A/Ds integrated into an FPGA.

I expect to see more chiplet analog integration in FPGAs, as A/Ds are common in many subsystem designs, including sensors and wireless communications. We may never see the fully programmable analog FPGA, but analog integration can benefit FPGAs in the same way it helped microcontrollers in earlier generations.


This article was originally published on Planet Analog.

After spending a decade in missile guidance systems at General Dynamics, Don Dingee became an evangelist for VMEbus and single-board computer technology at Motorola. He writes about sensors, ADCs/DACs, and signal processing for Planet Analog.


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